txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 16

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

MICROPROCESSOR INTERFACE
MAD(7-0)
POHDIS
Symbol
Symbol
AISIND
RESET
RD/WR
HIGHZ
D(7-0)
A(7-0)
PTEN
SEL
RD
AS
Pin No.
Pin No.
69-65
63-61
49-47
45-41
19
24
18
59
55
56
2
1
I/O/P
I/O/P
I/O
O
I
I
I
I
I
I
I
I
TTL8mA
TTLp
TTLp
TTLp
TTLp
Type
Type
TTL
TTL
TTL
TTL
TTL
Path Overhead Byte Processing Disabled: A low disables
the insertion of the POH bytes (they are tri-stated) into the SPE
from either the memory map RAM or the POH interface. It also
disables the processing of the POH bytes in the receive direc-
tion and their subsequent actions.
Receive AIS Indication Output: A low indicates that 140
Mbit/s AIS is being generated in the receive path. This pin is
disabled when the BSAISE control bit=1 and the RLAISD
alarm=1. However, when the L4M generates a receive line AIS,
this pin will go low even if BSAISE=1 and RLAISD=1.
High Impedance Enable: A low causes all output and
bi-directional pins to three-state for test purposes.
Pointer Tracking Enable: A high enables the internal pointer
tracking feature. The pointer tracking feature determines the
starting location of J1 in the dropped signal. The C1 pulse must
be provided as the DC1, or DC1J1 signal. The J1 pulse must
not be provided. The DSPE lead is ignored when the pointer
tracking machine feature is enabled. A low requires the DC1J1
and DSPE signals to be provided as inputs.
Hardware Reset: A low clears all performance counters, and
presets the internal FIFOs and counters. All control bits (10H-
1FH) are preset to 0 except for bit 3 of register 13H and bit 0 of
registers 1AH and 1BH. These 3 bits are preset to 1. This pulse
must be present for a minimum of 200 nanoseconds. Note: The
L4M requires approximately 1 microsecond upon power-up for
stabilization before a low can be applied to this pin.
Address Bus (Motorola/Intel Buses): These are address line
inputs that are used for accessing a RAM location for a read/
write cycle. A0 is the least significant bit. High is logic 1.
Address Select (Multiplex Bus): A low is used for address
select when the multiplex bus mode is selected.
Data Bus: Bi-directional data lines used for transferring data.
D0 is the least significant bit. Can also be used as multiplexed
address and data bus with Motorola interface. High is logic 1.
Select: A low will enable data transfers between the processor
and the L4M RAM during a read/write cycle.
Read (Intel mode) or Read/Write (Motorola mode):
Intel Mode - An active low signal generated by the microproces-
sor for reading the L4M RAM locations.
Motorola and multiplex Mode - An active high signal generated
by the microprocessor for reading the L4M RAM locations. An
active low signal is used to write to L4M RAM locations.
DATA SHEET
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Name/Function
Name/Function
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M