txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 59

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Ring Configuration
Figure 27 shows two L4M devices arranged in a ring configuration. The two L4Ms exchange path FEBE and
RDI information using the alarm indication port. The receive alarm indication port clock and framing pulse are
shared with the receive POH byte interface clock and framing pulse signals. This feature is disabled when an
active low is placed on the POHDIS lead. Data (RAIPD), as a repetitive byte, is clocked out of the L4M using
the path overhead interface clock (RPOHC). The path overhead frame pulse RPOHF indicates the start of the
repetitive data byte (RAIPD).
In normal operation, receive alarm indication port data (RAIPD) is connected to its mate transmit alarm indica-
tion port (TAIPD). The receive clock (RPOHC) is connected to transmit clock TAIPC at its mate, and the receive
framing pulse RPOHF is connected to the transmit frame pulse input (TAIPF). Likewise, the mate L4M’s receive
data is connected to the transmit alarm interface port. The clock present at TAIPC is monitored for operation.
An alarm indication port loss of clock alarm causes the FEBE count to be transmitted as 0, and RDI to be
transmitted as 0. Writing a 1 to the RING control bit selects the ring mode of operation.
The alarm indication byte is sent in the following way:
The byte is repeated nine times.
The information sent via the alarm indication port is:
- FEBE count
- Path RDI/FERF Indication whose value is set by:
- Received active low on the external AIS lead (XAIS alarm).
- Received E1 byte indication (E1AIS), and control bit EAPE is a 0.
- External ISTAT Pin (XISTAT) alarm, when control bit EAPE is a 1.
- External PAIS Pin (XPAIS) alarm, when control bit EAPE is a 1.
- Drop bus loss of J1 (DBLOJ1) when PTEN is low.
- Receive loss of pointer (RLOP) alarm when PTEN is high.
- Receive path AIS (RPAIS) alarm when PTEN is high.
- Path Signal Label Enable control bit (PSLEN) is a 1, and either a PSLERR or C2EQ0 alarm
- Control bit J1TEN is a 1, and a J1TIM alarm occurs.
- Control bit J1LEN is a 1, and a J1LOL alarm occurs.
occurs.
B3 Count
Bits 1-4
Path RDI
Bit 5
DATA SHEET
- 59 -
0
Bit 8
0
1
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M