txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 67

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

CONTROL REGISTER BIT DESCRIPTIONS
Address
10
Bit
7
6
5
4
3
2
1
POHEUQ
TESTB3
XRDIEN
Symbol
TINVC
TLAIS
EXOB
RING
Transmit Invert Line Clock: A 0 enables byte- or nibble-wide data
(TXDn) to be clocked into the L4M on positive transitions of the clock
(TXC). A 1 enables byte- or nibble-wide data to be clocked in on nega-
tive transitions of the clock.
Transmit Line AIS: A 1 enables the L4M to generate and insert an all
ones line signal (140 Mbit/s AIS) in the transmit direction, independent
of the state of the enable AIS bits and alarms. Transmit line AIS is gener-
ated under the following conditions:
- External loss of signal alarm (EXTLOS) when EAISEN is a 1,
- Loss of transmit clock alarm (TLOC) when TCAISEN is a 1,
- Loss of 140 Mbit/s frame alignment when LFAISE is a 1,
- Microprocessor writes a 1 to this bit position.
Path Protected Ring Mode: The L4M must be connected to a mate
L4M for this mode. A 1 enables the Transmit Alarm Indication Port to
control the FEBE (when FEBEEN=1) and RDI (when RDIEN=1) that are
transmitted in the G1 byte.
External "O"-bit Interface: A 1 enables the Overhead Communication
Channel data interface for transmitting the 90 overhead communication
channel bits ("O"-bits) specified in the 140 Mbit/s SDH/SONET format.
The interface bits are inserted asynchronously into the SDH/SONET for-
mat with respect to the nine subframes. A 0 causes zeros to be transmit-
ted for all of the "O"-bits.
Test B3 Byte: A 1 enables a microprocessor-written byte (location 68H)
to be the transmitted B3 byte. A 0 enables the microprocessor-written
byte in location 68H to work as a B3 error mask. A 1 written into one or
more bit positions will cause that bit position to be transmitted inverted
from its calculated value, until the bit position is written with a 0.
External RDI Enable: A 1 in this bit and the RDIEN bit enables a path
RDI (bit 5 in G1) to be generated and transmitted when a high is placed
on the STAI pin. A 0 disables the logic level placed on the STAI pin from
controlling the state of path RDI.
POH Bytes Enabled During Unequipped Status: This bit works in
conjunction with control bit TUNEQ for generating an unequipped chan-
nel. The Path Overhead Byte enable feature must be enabled (POHDIS
lead is high).
TUNEQ POHEUQ
0
1
1
X
0
1
DATA SHEET
- 67 -
Normal Operation
Unequipped Channel. POH and payload bytes are
transmitted as 0.
Supervisory Unequipped Channel. POH enabled.
Payload bytes transmitted as 0.
Action
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M