txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 10

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

SDH/SONET ADD BUS INTERFACE
Symbol
(n=7-0)
AC1J1
ASPE
ACLK
APAR
ADD
ADn
AC1
116-113
111-108
Pin No.
121
123
119
122
117
120
I/O/P
I/O
I/O
I/O
I/O
O
O
O
TTL4mA
TTL4mA
TTL4mA
TTL4mA
TTL4mA
TTL4mA
TTL4mA
Type
Add Bus Clock: The add clock is used for build timing, trans-
mit FIFO, and for sourcing the add bus byte-wide data (AD7-
AD0) and parity (APAR), when add bus timing is selected.
When external timing or drop timing mode is selected, this sig-
nal becomes an output. The add bus clock rate is 19.44 MHz.
Add Bus C1J1 Indicator: The C1 pulse is an active high, one
clock cycle wide, timing pulse that identifies the starting loca-
tion of the first C1 byte time slot in the STM-1 or STS-3c frame.
The C1 pulse may be provided on a separate lead (AC1) when
the add bus timing mode is selected. A J1 pulse, also one
clock cycle wide, identifies the starting location of the J1 byte
in the AU-4 VC-4 or STS-3c SPE signal when the POH bytes
are used. When the POH feature is disabled, the J1 pulse is
not required. When external timing or drop timing is enabled
this signal becomes an output. The C1J1 pulses correspond to
the C1 and J1 bytes present on AD(7-0). When a 1 is written to
control bit AC1EN, the C1 pulse may be provided on a sepa-
rate lead (AC1) instead of in the AC1J1 signal.
Add Bus Parity Bit: This output bit represents the odd parity
calculation for each data byte (and SPE and C1J1, including
AC1, when they are outputs). When a 1 is written to control
bit PARDO, parity is calculated for the data byte only. APAR is
not calculated over the unused TOH Byte times.
Add Bus SPE Indicator: An input signal in add timing mode
that is high during the AU-4/STS-3c SPE time. When the exter-
nal timing or drop timing modes are enabled, this signal
becomes an output.
Add Data Byte: Byte-wide data that corresponds to the AU-4/
STS-3c signal to be placed on the add bus. The first bit trans-
mitted corresponds to AD7 (pin 116). Data is three-stated dur-
ing periods of no activity (e.g., during unused TOH times).
Add Indicator: An active low signal that identifies the time
slots corresponding to the output data (AD7-AD0).
Add Bus C1 Pulse: This lead provides the C1 pulse as an
output when the drop bus timing or external timing modes are
enabled, and when the AC1EN control signal is a 1. The
AC1J1 signal will contain the C1 pulse. When the add bus tim-
ing mode is enabled, this lead may be used as the C1 input,
independent of the AC1EN control bit. This signal is or-gated
internally with the AC1J1 signal in the add bus timing mode to
form a composite C1J1signal. If this signal lead is not used in
the add bus timing mode, it must be grounded.
DATA SHEET
- 10 -
Name/Function
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M