txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 51

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Boundary Scan
Introduction
The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified
by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides
observability and controllability for the L4M device’s interface pins. The Boundary Scan Block consists of a Test
Access Port (TAP) controller, instruction and data registers, and a boundary scan path bordering the input and
output pins. The boundary scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode
Select (TMS), Test Data Input (TDI) and Test Reset (TRS) and a Test Data Output (TDO) output signal.
The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select
(TMS) signal, and sends control signals to the internal scan paths. The scan path architecture consists of a
two-bit serial instruction register and two or more serial data registers. The instruction and data registers are
connected in parallel between the serial Test Data Input (TDI) and Test Data Output (TDO) signals. The Test
Data Input (TDI) signal is routed to both the instruction and data registers and is used to transfer serial data
into a register during a scan operation. The Test Data Output (TDO) is selected to send data from either regis-
ter during a scan operation.
When boundary scan testing is not being performed the boundary scan register is transparent, allowing the
input and output signals to pass to and from the L4M device’s internal logic, as illustrated in Figure 24. During
boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow
the device to be controlled and observed via scan operations. A timing diagram for the boundary scan feature
is provided in Figure 21.
Boundary Scan Support
The maximum frequency the L4M device will support for boundary scan is 10 MHz. The L4M device performs
the following boundary scan test instructions:
EXTEST Test Instruction:
One of the required boundary scan tests is the external boundary test (EXTEST) instruction. When this
instruction is shifted in, the L4M device is forced into an off-line test mode. While in this test mode, the test bus
can shift data through the boundary scan registers to control the external L4M input and output leads.
SAMPLE/PRELOAD Test Instruction:
When the SAMPLE/PRELOAD instruction is shifted in, the L4M device remains fully operational. While in this
test mode, L4M input data, and data destined for device outputs, can be captured and shifted out for inspec-
tion. The data is captured in response to control signals sent to the TAP controller.
BYPASS Test Instruction:
When the BYPASS instruction is shifted in, the L4M device remains fully operational. While in this test mode, a
scan operation will transfer serial data from the TDI input, through an internal scan cell, to the TDO pin. The
purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a
single clock delay.
- EXTEST
- SAMPLE/PRELOAD
- BYPASS
DATA SHEET
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Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M