txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 6

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

L4M
DATA SHEET
TXC-03456
addition, the desynchronizer pointer offset counter (9 bits plus sign value) is provided in the memory map for a
microprocessor read, if required.
The output of the Desynchronizer Block is connected to the L4M Output Block, Receive Frame Alignment
Detector Block and Receive AIS Detector Block. The 140 Mbit/s receive line signal is monitored by the Receive
Frame Alignment Detector Block for ITU-T G.751 frame alignment and the Distant Alarm Status. A Distant
alarm is defined as a 1 in bit 13 of the G.751 frame format. This alarm can generate an interrupt indication
when enabled. When frame alignment is established, framing errors are counted in a 16-bit performance
counter.
The 140 Mbit/s line signal is also monitored for an Alarm Indication Signal (AIS). The AIS detection circuit can
be enabled to work in conjunction with the frame alignment circuit. An AIS condition is reported as an alarm,
and can generate an interrupt when enabled. The Receive Frame Alignment Detector and Receive AIS Detec-
tor Blocks are disabled when the bit stuffing approach for generating 140 Mbit/s AIS is enabled and when the
L4M generates a receive line AIS. AIS using a bit stuffing approach is implemented in the Decode Block prior
to the Desynchronizer Block.
A byte-wide or nibble-wide 139.264 Mbit/s signal (RXDn) is provided as an output from the Output Block. A nib-
ble interface is selected by placing a high on the lead designated as NIB. Data is normally clocked out of the
L4M on negative transitions of the clock signal RXCO. A control bit is provided which enables data to be
clocked out of the L4M on positive transitions of the clock.
External access to the Path Overhead bytes is provided by the POH I/O Block. The nine receive POH bytes
present in the serial data channel (RPOHD) are clocked out on negative transitions of the gapped clock
(RPOHC). A framing pulse (RPOHF), one clock cycle wide, identifies the starting location of the POH bytes,
with bit 1 in the J1 byte. In the transmit direction, a gapped clock (TPOHC), and framing pulse (TPOHF) are
provided. Serial data containing the POH bytes is clocked into the L4M on positive transitions of the clock. The
B3 byte is present in the serial bit stream, but it is ignored by the L4M, and is recalculated. The framing pulse is
one clock cycle wide and identifies the starting location of the POH bytes, with bit 1 in the J1 byte.
An external AIS input is provided for generating a received 140 Mbit/s AIS and an RDI indication, if the POH
bytes are processed externally.
The Overhead Communications Channel I/O block provides an asynchronous interface for the 90 "O"-bits
found in the SDH/SONET format. Serial data (ROCHD) which contains the "O"-bits, is clocked out of the L4M
on negative transitions of the gapped clock (ROCHC). The received "O"-bits are not synchronized with the
starting location of the frame. In the transmit direction, the "O"-bits (TOCHD) are clocked into the L4M by the
gapped output clock (TOCHC).
The Alarm Indication Port data output signal (RAIPD), consisting of the FEBE count and RDI indication, is
clocked out of the L4M on negative transitions of the receive POH clock (RPOHC). The serial data consists of
nine bytes each frame. The first four bits correspond to the FEBE count, which has been derived from the B3
BIP-8 parity check. The next bit, bit 5, corresponds to the RDI indication. Bits 6 and 7 are set to 0, while bit 8 is
set to a 1. The received POH framing pulse (RPOHF) identifies the starting location of bit 1 in the first byte. In
the transmit direction, the received serial data, framing pulse, and clock from the mate L4M become the data
input (TAIPD), framing pulse input (TAIPF), and clock input (TAIPC). When the ring mode is selected, the mate
L4M FEBE count and RDI indication are transmitted in the G1 byte.
An upstream AIS indication may be inputted into the L4M using the E1 byte in the Transport (Section) Over-
head bytes, or the external ISTAT, PAIS, and STAI pins. The upstream AIS indication can generate a 140
Mbit/s AIS, and a transmit RDI indication.
The L4M supports three types of microprocessor interfaces: Intel microprocessor with separate address and
data buses, Motorola microprocessor with separate address and data buses, and a Motorola microprocessor
with a multiplexed address/data bus interface.
The Boundary Scan block provides a mechanism for external access to the input and output pins of the device,
so that they may be observed and tested. The structure and operation of this block are described in the Opera-
tion section.
TXC-03456-MB
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Ed. 1A, January 2000