txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 40

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

OPERATION
The operations section is divided into two major sections: Internal Device Operation, and External Device
Interfaces.
INTERNAL DEVICE OPERATION
Timing Modes
The L4M supports the following timing modes: drop bus, add bus, and external timing modes. In the drop bus
timing mode, the drop bus clock (DCLK) and the C1 pulse (DC1J1 or DC1) before or after framing reference
compensation, provide the time base for deriving the add bus signals which consist of clock (ACLK), data
(AD(7-0)), C1 and J1 indicator (AC1J1 and AC1), SPE indicator (ASPE), add indicator (ADD), and parity
(APAR). The add side J1 pulse is derived internally. The add bus starting location for the SPE may have a
pointer value equal to 0 or 522.
In the add bus timing mode, add bus timing signals are independent of the drop bus signals. Add bus timing is
derived from add bus input signals which consists of a clock (ACLK), C1 and J1 indicator (AC1J1 and AC1),
and SPE indicator (ASPE). The output signals consists of data (AD(7-0)), add indicator (ADD), and parity
(APAR). The starting location of the SPE (J1 byte) is determined by the input J1 pulse (AC1J1), and SPE indi-
cator (ASPE).
In the external timing mode, the external timing signals are independent of the drop bus timing. The external
timing signals consist of an external clock (EXTC) and optional frame reference pulse (EXC1). The L4M can
also compensate for up to one frame of offset delay for the external C1 pulse. Add bus output timing is derived
from the two external signals and consists of a clock (ACLK), C1 and J1 indicator (AC1J1 and AC1), SPE indi-
cator (ASPE), data (AD(7-0)), add indicator (ADD), and parity (APAR). The add bus starting location for the
SPE may have a pointer value equal to 0 or 522.
The three timing modes are selected using two control pins, designated as DROPT (pin 35) and ENABT (pin
36). The following table lists the control lead states for selecting the timing mode.
Receive C1 Reference Delay
When the pointer tracking feature is enabled by placing a high on the PTEN lead (pin 2), and control bit
RC1DC (bit 3 in 18H) is written with a 1, a 12-bit register location (19H and 18H) is enabled which can com-
pensate for up to 2429 positions (270 columns x 9 rows) for a dropped C1 reference pulse. For example, if a
binary 0 is written into the 12-bit register by the microprocessor, the C1 pulse (in DC1J1 or DC1) must be in the
C11 time slot (the correct time slot). When the binary value of 1 is written into the 12-bit register, it is assumed
that the C1 pulse is shifted one time slot (one clock cycle) into the time slot that corresponds to the C12 byte.
This means that the starting point for the frame reference should be one byte earlier. Values written into the
12-bit register greater than 2429 will be counted as a delay equal to 0.
DROPT pin
High
Low
X
ENABT pin
High
Low
Low
Add Bus Timing
External Timing
Drop Bus Timing
DATA SHEET
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Timing Mode
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M