txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 57

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

EXTERNAL DEVICE OPERATION
Phase-Locked Loop
The phase-locked loop (PLL) circuit for the L4M is shown in Figure 25. The bandwidth (BW Hz) of the PLL is
given by the following equation.
where,
The bandwidth of the PLL is equal to 7.7 Hz.
To ensure that the L4M meets the jitter performance outlined in the ETS1015 document, an adaptive FIFO leak
rate algorithm must be employed to dynamically adjust the value written to the FLR register (1AH). An applica-
tion note on this subject entitled “Jitter Test results for the L4M device - Application Note”, document number
TXC-03456-0001-AN, Edition 1.0, February 7, 1995 is available upon request.
L4M
TXC-03456
CTRL
CTRL
RXCI
BW = K
Ko = (30ppm/v) x (139.264 Hz/ppm) x (2 )
Kd = 5v/[(2 ) x (256)]
Kh = 39/[2 x (15 + 36/2)] = 0.591
14
15
21
d
K
Termination
o
K
resistor
h
/2
TTL
36K
36K
TTL
15K
by 4 for Nibble I/O
by 8 for Byte I/O
Figure 25. Phase-Locked Loop
+2.0V
Divided
0.1 F
+
-
39K
741
DATA SHEET
- 57 -
2 F
ECL
2.2K
e.g., Connor-Winfield EDV54-120-31
139.264 MHz
30 ppm
VCXO
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M