TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 98

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

PF
(0030H)
PFFC
(0032H)
3.5.17
Note: Read-modify-write is prohibited for the registers PFFC.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Port F (PF0 to PF7)
output 1.
controller (SDCKE, SDCLK, SDLDQM, SDUDQM,
(SSCLK). Above setting is used the function register PFFC.
Port F is an 8-bit output port. Resetting sets the output latch PF to 1, and PF0 to PF7 pin
In addition to functioning as output port, port F also function as output pin for SDRAM
Reset
Always write
“0”.
Output latch
Function control
PFFC write
PF7
(on bit basis)
7
7
1
−
0
PF write
PF read
0: Port
1: SDCLK
PF6F
PF6
Figure 3.5.46 Register for Port F
6
6
1
1
SDUDQM, SDCKE, SDCLK
Figure 3.5.45 Port F
SDRAS
0: Port
1: SDCKE
Port F Function Register
A
B
PF5F
PF5
91C820A-96
5
5
Port F Register
1
0
,
S
SDCAS
0: Port
1: SDUDQM
Output buffer
PF4F
,
PF4
SDWE
4
4
1
0
R/W
, SDLDQM,
W
0: Port
1: SDLDQM
PF3F
PF3
3
3
1
0
SDWE
0: Port
1: SDWE
PF2F
PF0 (
PF1 (
PF2 (
PF3 (SDLDQM)
PF4 (SDUDQM)
PF5 (SDCKE)
PF6 (SDCLK)
PF7
PF2
), and output pin for SSIO
2
2
1
0
SDWE
SDRAS
SDCAS
0: Port
1: SDCAS
PF1F
)
PF1
)
)
1
1
1
0
TMP91C820A
0: Port
1: SDRAS
2008-02-20
PF0F
PF0
0
0
1
0