TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 199

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TMP91xy20AFG

Manufacturer Part Number
TMP91xy20AFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy20AFG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M
Rom Combinations
8
Ram Combinations
8
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
77
Power Supply Voltage(v)
3.0 to 3.6
SCK pin output
SO pin output
Write
transmitted data
Figure 3.10.24 Maximum Data Transfer Frequency when External Clock Input Used
(1) Serial Clock
SCK pin
a.
Internal clock
External clock (<SCK2:0> = 111)
Clock source
signal is output to the outside on the SCK pin. When the device is writing (in
transmit mode) or reading (in receive mode), data cannot follow the serial clock
rate, so an automatic wait function is executed which automatically stops the
serial clock and holds the next shift operation until reading or writing has been
completed.
ensure the integrity of shift operations, both the high and low-level serial clock
pulse widths shown below must be maintained. The maximum data transfer
frequency is 2.3 MHz (when fc = 36 MHz).
SBI0CR1<SCK2:0> is used to select the following functions:
In internal clock mode one of seven frequencies can be selected. The serial clock
a
An external clock input via the SCK pin is used as the serial clock. In order to
t
SCKL
a
1
0
, t
SCKH
a
Figure 3.10.23 Automatic Wait Function
2
1
t
SCKL
a
> 8/fc
2
3
t
SCKH
a
5
a
7
6
91C820A-197
at prescaler clock = fc
a
Automatic wait function
8
7
b
b
1
0
b
1
2
c
b
4
b
6
5
b
7
6
b
8
7
c
1
0
c
2
1
TMP91C820A
2008-02-20
c
3
2

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