TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 245

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.14.4
3.14.4.1 Operation
Shift-Register Type LCD Driver Control Mode (SR type)
level and LCD size to control registers before start SR type.
data memory. After that LCDC transmits data of volume of LCD size to external LCD
driver through LCD personal data bus (LD7:0). At this time, control signals (D1BSCP
etc.) connected LCD driver output specified waveform synchronizes with data
transmission. After finish data transmission, LCDC cancels the bus release request
and CPU will restart. LCD controller use LCDCK for generation waveform of D3BFR,
DLEBCD and D2BLP pins. LCDCK select TAOUT that be outputted from low
frequency oscillator (fs): 32.768kHz or internal TMRA23 by setting EMCCR0
<TA3LCDE> register. <TA3LCDE> is cleared to “0” by external reset, and low
frequency oscillator (fs) is set.
Note: When set LCDC to SR type, during data reading (during DMA operation), CPU is
Set the mode of operation, start address of display data save memory, gray-scale
After start it LCDC outputs bus release request to CPU and read data from display
stopped by internal BUSREQ signal. When using SR type LCDC, programmer
need to care the CPU stop time. For detail, see the Table 3.14.8.
91C820A-243
TMP91C820A
2008-02-20