TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 125

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

TMRA0 comparator match
detect signal
TMRA0 comparator match
detect signal
TA1OUT
INTTA0
INTTA1
Value of up counter
(UC1, UC0)
(2) 16-bit timer mode
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
set TA01MOD<TA01M1:0> to 01.
TMRA1, regardless of the value set in TA01MOD<TA01CLK1:0>. Table 3.7.2 shows
the relationship between the timer (Interrupt) cycle and the input clock selection.
value in the registers:
matches TA0REG, though the up counter UC0 is not be cleared.
comparator pulse on which the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparator
TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
Setting example: To generate an INTTA1 interrupt every 0.22 s at fc = 36 MHz, set the timer registers TA0REG
Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
If φT16 ((2
0.22 s ÷(2
(e.g. set TA1REG to F4H and TA0REG to 24H).
As a result, INTTA1 interrupt can be generated every 0.23 [s].
The comparator match signal is output from TMRA0 each time the up counter UC0
In the case of the TMRA1 comparator, the match detect signal is output on each
Figure 3.7.12 Timer Output by 16-Bit Timer Mode
7
7
/fc)s ≈ 62500 = F424H
/fc)s at 36 MHz) is used as the input clock for counting, set the following
and TA1REG as follows:
* Clock state
0080H
91C820A-123
0180H
0280H
System clock:
Clock gear:
Prescaler clock: f
0380H
High frequency (fc)
1 (fc)
FPH
0480H
Inversion
0080H
TMP91C820A
2008-02-20