TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 72

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.5.6
Port Z (PZ0 to PZ3)
set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ
to 1.
the CPU’s control/status signal.
output latch register <PZ0> to 0 outputs the
from the PZ0 pin even when the internal addressed. If the output latch register <PZ0>
remains 1, the
and PZ1 pins to the following function pins.
Port Z is an 4-bit general-purpose I/O port (P50 and P51 are used for output only). I/O is
In addition to functioning as a general-purpose I/O port, port Z also functions as I/O for
When PZ0 pin is defined as
Resetting initializes PZ2 and PZ3 pins to input mode with pull-up resistor.
Setting the AM1 and AM0 pins as shown below and resetting the device initialize PZ0
Reset
Function control
(on bit basis)
PZFC write
AM1 AM0
PZ write
PZ read
0
0
1
1
Output
latch
RD
0
1
0
1
Internal address area
strobe signal is output only when the external address are is accessed.
PZ0F
PZ1F
Figure 3.5.11 Port Z (PZ0)
1
1
–
0
A
B
Function Setting after Reset is Released
Don’t use this setting
RD
91C820A-70
RD
PZ0 function
Output port
S
strobe signal output mode (<PZ0F> = 1), clearing the
RD
RD
Output buffer
pin
pin
RD
Don’t use this setting
strobe (Used for the peused static RAM)
PZ1 function
Output port
PZ0 (
WR
WR
pin
pin
RD
)
TMP91C820A
2008-02-20