TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 214

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(5) AD conversion time
(6) Storing and reading the results of AD conversion
Analog Input Channel
channel.
store the results of AD conversion. (ADREG04H/L to ADREG37H/L are read-only
registers.)
successively in registers ADREG04H/L to ADREG37H/L. In other modes the AN0 and
AN4, AN1 and AN5, AN2 and AN6, and AN3 and AN7 conversion results are stored in
ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L respectively.
registers, which are used to hold the results of AD conversion.
conversion data storage flag. The storage flag indicates whether the AD conversion
result register has been read or not. When a conversion result is stored in the AD
conversion result register, the flag is set to 1. When either of the AD conversion result
registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0.
ADMOD0<EOCF> to 0.
Table 3.11.3 Correspondence between Analog Input Channels and
84 states (4.7 µs at f
The AD conversion data upper and lower registers (ADREG04H/L to ADREG37H/L)
In channel fixed repeat conversion mode, the conversion results are stored
Table 3.11.3 shows the correspondence between the analog input channels and the
<ADRxRF> bit0 of the AD conversion data lower register is used as the AD
Reading the AD conversion result also clears the AD conversion end flag
(Port 8)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AD Conversion Result Registers
Conversion Modes
Other than at Right
FPH
91C820A-212
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
= 36 MHz) are required for the AD conversion of one
AD Conversion Result Register
Channel Fixed Repeat
Conversion Mode
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
(<ITM0> = 1)
TMP91C820A
2008-02-20