TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 146

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

with PB1
Shared
RXD2
f
φ T0
SYS
SC2MOD0
<RXE>
φ T0
φ T2
φ T8
φ T32
RXDCLK
RB8
Serial clock generation circuit
Receive buffer 1 (Shift register)
<BR2CK1:0>
2
Receive buffer 2 (SC2BUF)
BR2CR
(Only UART ÷ 16)
φ T2
4
Prescaler
Receive
Receive
counter
<BR2S3:0>
control
8
BR2CR
φ T8 φ T32
16 32 64
Figure 3.9.4 Block Diagram of the Serial Channel 2
Baud rate
generator
<BR2ADDE>
BR2CR
BR2ADD
<OERR><PERR><FERR>
SC2MOD0
<WU>
<BR2K3:0>
Internal data bus
<PE>
Parity control
SC2CR
Error flag
÷ 2
SC2CR
91C820A-144
Serial channel
<EVEN>
(from TMRA0)
interrupt
TA0TRG
control
SC2MOD0
<SC1:0>
SC2CR
<IOC>
I/O
interface mode
UART
mode
SC2MOD0
TXDCLK
<SM1:0>
TB8
Transmission buffer (SC2BUF)
(Only UART ÷ 16)
Transmission
Transmision
counter
control
SIOCLK
TMP91C820A
INT request
INTRX2
INTTX2
2008-02-20
TXD2
Shared
with PB0