TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 292

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(5) Limitation point to use SDRAM
(Example of calculation)
under below and take care.
Condition:
There are some points to notice when using SDRAMC. Please refer to the section
1) WAIT access
2) Execution of SDRAM command before HALT instruction (SR(Self refresh)-Entry ,
3) AR (Auto Refresh) interval time
(14 × refresh interval time; in Auto Refresh function controlled by SDRAM
controller).
has (SR- Entry, Initialize).
insert over 10 bytes NOP or other 10 bytes instructions before HALT instruction.
specification that is minimum operating clock and minimum Refresh interval time.
system with special care for Auto Refresh interval time.
Auto Refresh interval time, because it might not meet the A.C specification of
SDRAM by stopping Auto Refresh.
4096 times/64 ms
Initialize , Mode-set)
When using SDRAM, it is added some limitation of access to all other memories.
Under the N-WAIT setting of this MCU, it is prohibited inserting the time over
It requires execution time (a few states) to execute the command that SDRAMC
Therefore when executing HALT instruction after the SDRAM command, please
When using SDRAM, CPU clock must be set suitable speed for SDRAM’s
When using SDRAM under slow mode or down the Clock Gear, please design the
And please set Auto Refresh interval time after adding 10 states to distributed
f
SYS
64ms/ 4096 times = 15.625µs/1 time = 281.25state/1 time
281.25 – 10 = 271.25 state/less than 1 time is needed
= 18MHz, SDRAM specification of distributed Auto Refresh interval time =
91C820A-290
247 state is needed
TMP91C820A
2008-02-20