TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 270

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.14.5
3.14.5.1 Operation
Figure 3.14.19 Example of Access Timing for RAM Built-in Type LCD Driver (Wait = 0)
RAM Built-in Type LCD Driver Control Mode (RAM type)
LCDC outputs chip select signal to LCD driver connected to the outside from control
pin (D1BSCP etc.). Therefore control of data transmission numbers corresponding to
LCD size is controlled by instruction of CPU. There are 2 kinds of address of LCD
driver in this case, and which is chosen determines by LCDCTL <MMULCD> register.
display data register in LCD driver at the time of <MMULCD> = “0”. Please make the
transmission place address at this time into either of FE0H to FE7F. (SEQUENTIAL
ACCESS TYPE: See Table 3.14.3)
= “1”.
3C0000H to 3FFFFFH to four area for every 64 Kbytes. (RANDOM ACCESS TYPE:
See Table 3.14.4)
Data transmission to LCD driver is executed by move instruction of CPU.
After setting mode of operation to SFR, when move instruction of CPU is executed
It corresponds to LCD driver which has every 1 byte of instruction register and
It corresponds to address direct writing type LCD driver at the time of <MMULCD>
The transmission place address at this time can also assign the memory area of
System clock: f
D1BSCP, D2BLP,
D3BFR, DLEBCD
A23 to A0
D7 to D0
SYS
R/W
91C820A-268
[Write cycle]
Data-out
[Read cycle]
Data-in
TMP91C820A
2008-02-20