TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 57

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(6) Notes
Note: The following instructions or pin input state changes are equivalent to instructions that
INT0: Instructions which switch to level mode after an interrupt request has been generated in
INTRX: Instructions which read the receive buffer.
;INT0 level mode
INTRX
independently. Therefore, immediately before an interrupt is generated, if the CPU
fetches an instruction that clears the corresponding interrupt request flag, the CPU
may execute the instruction that clears the interrupt request flag between accepting
and reading the interrupt vector. In this case, the CPU reads the default vector 0008H
and reads the interrupt vector address FFFF08H.
after a DI instruction. And in the case of setting an interrupt enable again by EI
instruction after the execution of clearing instruction, execute EI instruction after
clearing and more than 1 instructions (ex. “NOP” × 1 time). If placed EI instruction
without waiting NOP instruction after execution of clearing instruction, interrupt will
be enable before request flag is cleared.
execution of POP SR instruction, disable an interrupt by DI instruction before
execution of POP SR instruction.
attention.
The instruction execution unit and the bus interface unit of this CPU operate
To avoid the above problem, place instructions that clear interrupt request flags
In the case of changing the value of the interrupt mask register <IFF2:0> by
In addition, take care as the following 2 circuits are exceptional and demand special
clear the interrupt request flag.
edge mode.
The pin input changes from high to low after an interrupt request has been generated in
level mode. (H → L)
In level mode INT0 is not an edge-triggered interrupt. Hence, in level
mode the interrupt request flip-flop for INT0 does not function. The
peripheral interrupt request passes through the S input of the flip-flop
and becomes the Q output. If the interrupt input mode is changed from
edge mode to level mode, the interrupt request flag is cleared
automatically.
If the CPU enters the interrupt response sequence as a result of INT0
going from 0 to 1, INT0 must then be held at 1 until the interrupt
response sequence has been completed. If INT0 is set to level mode
so as to release a halt state, INT0 must be held at 1 from the time
INT0 changes from 0 to 1 until the halt state is released. (Hence, it is
necessary to ensure that input noise is not interpreted as a 0, causing
INT0 to revert to 0 before the halt state has been released.)
When the mode changes from level mode to edge mode, interrupt
request flags which were set in level mode will not be cleared.
Interrupt request flags must be cleared using the following sequence.
The interrupt request flip-flop can only be cleared by a reset or by
reading the serial channel receive buffer. It cannot be cleared by
writing INTCLR register.
DI
LD (IIMC), 00H
LD (INTCLR), 0AH ; Clears interrupt request flag.
NOP
EI
91C820A-55
; Switches interrupt input mode from level
; Wait EI instruction
mode to edge mode.
TMP91C820A
2008-02-20