TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 661

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.7
18.7.1
18.7.2
18.7.3
18.7.4
18.7.5
Notes on Using the USB Host Controller
<PLLSEL> must be set to "1".
of ±50ppm or less to comply with the USB specification.
tion depending on the implementation environment, conditions and variations.
PEND state. Then turn off Vbus.
connection is discontinued and the CPU/DMA has higher priority for access. The USBHC is reconnected
when the CPU/DMA access is completed. Note that if the disconnection of the USBHC caused by the CPU/
DMA takes long, it may cause problems in USB transfer. Specifically, in case IN transfer, the CPU/DMA
must complete to access in the period where the 64-byte FIFO contained in the USBHC becomes full (within
42.66μs).
The PLL is not active after reset release. Therefore, before accessing the USB Host, the CGPLLSEL
To generate a clock for the USBHC, we recommend using a 12-MHz crystal oscillator with an accuracy
Note that a USB clock generated by the on-chip PLL may not satisfy the requirements of the USB specifica-
Before entering SLOW Mode and Low Power Consumption Modes, the USBHC must be placed in the SUS-
The D+ and D- pins must be pulled-down.
If the CPU/DMA accesses the RAM0 or the RAM1 when the USBHC is already accessing it, the USBHC
Setting the USB Clock
Oscillator Recommendation
Entering SLOW Mode and Low Power Consumption Modes
When not using USB
Competing access to the RAM0 and the RAM1
(Example Software setting)
1
2
3
4
5
6
7
8
Disable interrupt
HcCommandStatus
HcControl
HcBCR0
Output "0" to PG6
Setup to shifting low power consumption and oth-
ers.
Stop PLL
Execute WFI instruction
<HCR>
<HCFS>
<TRANS_SUSP>
=
=
=
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1
1 1
1
(Write)
(Read)
(Write)
: Software reset of the USB host controller
: Check the transition to the SUSPEND state.
: Change the state of the D+ and D- pin to the SUSPEND
state
: Vbus OFF
: Stop of peripheral function, port setting, warm up setting
and so on. About shifting BACKUP mode, refer to that
section.
TMPM364F10FG