TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 596

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.6
Operation Mode
16.6.4
16.6.5
Figure 16-8 Flowchart of Setup of Test Loop Back Mode and Test Error Mode
acknowledge bit. No other CAN node is necessary for the operation.
test loop back mode, the CAN controller can transmit a message from a mailbox and receive it in another mail-
box. The setup for mailboxes is the same as in normal operation mode.
er 8 bits are concurrently written to both the transmit error counter (CANTEC) and the receive error counter
(CANREC). The maximum value that can be written into the error counters is 255. The error counter value
of 256 which forces the CAN controller into bus off mode can not be written.
In test loop back mode, the CAN controller can receive its own transmitted message and generates its own
The test loop back mode can be enabled or disabled only when the CAN controller is in suspend mode. In
In test error mode, writes to the CAN error counter register (CANCEC) are possible. The values of the low-
The test error mode can be enabled or disabled only when the CAN controller is in suspend mode.
Figure 16-8 shows the flowchart of the setup of test loop back mode and test error mode.
Test Loop Back Mode
Test Error Mode
Back to normal operation mode with
CAN is in normal operation mode:
enabled/disabled <TSTLB> and/or
CAN is in normal operation mode
with enabled/disabled test loop
<TSTERR>: set <SUR> to “0”
test loop back mode and
back and/or test error mode
Suspend mode request:
Setup <TSTLB> and/or
“1” enable,“0” disable
<CCR>=0 & <CCE>=0
<SUR>=0 & <SUA>=0
<TSTERR> bit:
test error mode
Enable/disable
<SUA> = 0 ?
<SUA> = 1 ?
End of setup;
Page 570
Yes
Yes
No
No
TMPM364F10FG