TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 565

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.4.11
31
30-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
where auto acknowledgement of remote frames is enabled (CANMBnID<RFH>="1"). Mailbox x enabling au-
tomatic acknowledgement starts message transmission automatically responding to received remote frames
and so may update the data field during message transmission (In such cases, updated data is output midway
through transmission). The update of the data field can be avoided by setting the <CDRx> bit to "1" and tem-
porarily suspending data transmission.
−
CDR30 to
CDR0
The change data request register CABCDR is effective when updating the data field of transmit mailbox x
Bit Symbol
Note:Mailbox 31 is receive-only mailbox.
CANCDR (Change Data Request Register)
CDR23
CDR15
CDR7
31
23
15
0
0
0
7
0
-
R
R/W
Type
CDR30
CDR22
CDR14
CDR6
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
Change data request (Each bit corresponds with mailboxes 30 to 0.)
When the <CDRx> bit of transmit mailbox x is set to "1", the transmit request of this mailbox x is ignored.
It means mailbox x for which the CANTRS<TRSx> bit and the <CDRx> bit are set will be excluded from
the internal arbitration range and will not be transmitted if transmission has not started. After the <CDRx>
bit is cleared to "0", mailbox x is back to be included in the internal arbitration range.
CDR29
CDR21
CDR13
CDR5
29
21
13
0
0
0
5
0
Page 539
CDR28
CDR20
CDR12
CDR4
28
20
12
0
0
0
4
0
CDR27
CDR19
CDR11
CDR3
27
19
11
Function
0
0
0
3
0
CDR26
CDR18
CDR10
CDR2
26
18
10
0
0
0
2
0
CDR25
CDR17
CDR9
CDR1
25
17
0
0
9
0
1
0
TMPM364F10FG
CDR24
CDR16
CDR8
CDR0
24
16
0
0
8
0
0
0