TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 19

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15. Consumer Electronics Control (CEC)
14.7 Control register of SIO mode..............................................................................................476
14.8 Control in SIO mode...........................................................................................................482
15.1 Outline.................................................................................................................................489
15.2 Block Diagram.....................................................................................................................490
15.3 Registers..............................................................................................................................491
15.4 Operations............................................................................................................................510
14.6.3
14.6.4
14.6.5
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
14.8.1
14.8.2
15.1.1
15.1.2
15.1.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
15.3.7
15.3.8
15.3.9
15.3.10
15.3.11
15.3.12
15.3.13
15.3.14
15.3.15
15.4.1
15.4.2
15.4.3
15.4.4
14.6.2.1
14.6.2.2
14.6.3.1
14.6.3.2
14.8.1.1
14.8.1.2
14.8.2.1
14.8.2.2
14.8.2.3
14.8.2.4
15.4.2.1
15.4.2.2
15.4.2.3
15.4.2.4
15.4.2.5
15.4.2.6
15.4.3.1
15.4.3.2
15.4.3.3
15.4.3.4
15.4.3.5
15.4.3.6
Transferring a Data Word.............................................................................................................................................469
Generating the Stop Condition......................................................................................................................................474
Restart Procedure...........................................................................................................................................................474
SBIxCR0(control register 0).........................................................................................................................................476
SBIxCR1(Control register 1)........................................................................................................................................477
SBIxDBR (Data buffer register)...................................................................................................................................478
SBIxCR2(Control register 2)........................................................................................................................................479
SBIxSR (Status Register)..............................................................................................................................................480
SBIxBR0 (Baud rate register 0)....................................................................................................................................481
Serial Clock...................................................................................................................................................................482
Transfer Modes..............................................................................................................................................................484
Reception.......................................................................................................................................................................489
Transmission..................................................................................................................................................................489
Precautions.....................................................................................................................................................................489
Register List...................................................................................................................................................................491
CECEN (CEC Enable Register)....................................................................................................................................492
CECADD (Logical Address Register ).........................................................................................................................493
CECRESET (Software Reset Register)........................................................................................................................494
CECREN (Receive Enable Register)............................................................................................................................495
CECRBUF (Receive Buffer Register)..........................................................................................................................496
CECRCR1 (Receive Control Register 1)......................................................................................................................497
CECRCR2 (Receive Control Register 2)......................................................................................................................499
CECRCR3 (Receive Control Register 3 )....................................................................................................................501
Sampling clock..............................................................................................................................................................510
Reception.......................................................................................................................................................................510
Transmission..................................................................................................................................................................519
Software Reset...............................................................................................................................................................524
CECTEN (Transmit Enable Register).........................................................................................................................503
CECTBUF (Transmit Buffer Register).......................................................................................................................504
CECTCR (Transmit Control Register).......................................................................................................................505
CECRSTAT (Receive Interrupt Status Register).......................................................................................................507
CECTSTAT (Transmit Interrupt Status Register)......................................................................................................508
CECFSSEL(CEC Sampling Clock Select Register)...................................................................................................509
Master mode
Slave mode
Master mode (<MST> = "1")
Slave mode (<MST> = "0")
Clock source
Shift Edge
8-bit transmit mode
8-bit receive mode
8-bit transmit/receive mode
Data retention time of the last bit at the end of transmission
Basic Operation
Preconfiguration
Enabling Reception
Detecting Error Interrupt
Details of reception error
Stopping Reception
Basic Operation
Preconfiguration
Detecting Transmission Error
Details of Transmission Error
Stopping Transmission
Retransmission
xi