TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 595

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.6.2
16.6.3
troller has entered into sleep mode, the CANGSR<SMA> bit is set to "1".
fer and sleep mode is active where the <SMA> bit is "1". Read values to all other registers deliver the value
0x0000. Write accesses to all registers, except the CANMCR register, will be denied.
the CANMCR register is detected, or there is any bus activity detected on the CAN bus with the CANMCR
<WUBA> bit set to "1". The CAN controller waits until detecting 11 consecutive recessive bits on the
CANRX input terminal, after it goes into bus active state. The walk-up message is invalid.
sion request reset CANTRR<TRRx> bits are cleared. The <SMR> bit and the <SMA> bit are cleared after
the CAN controller leaves sleep mode.
the CAN controller enters sleep mode after any of the following occurs:
idle, the current message transmission/reception is completed before suspend mode is activated. After the
CAN controller has entered suspend mode, the CANGSR<SUA> bit is set to "1".
nor acknowledgement will be sent. The error counters and the CANGSR<EP> bit will not be cleared either.
pend mode after the bus off recovery sequence is finished.
state or the inactive state, the CAN controller restarts the bus off recovery sequence.
Sleep mode is requested by a write of "1" to the <SMR> bit in the CANMCR register. After the CAN con-
The read value of the CANGSR register is 0xF040. This means that there is no message in the transmit buf-
The CAN controller cancels sleep mode (wakes up) and starts the power-up sequence if a write access to
In sleep mode, the CAN error counters and all transmission request set CANTRS<TRSx> bits and transmis-
If sleep mode is requested while the CAN controller is transmitting a message (CANMCR<SMR>="1"),
The suspend mode is requested by writing "1" to the CANMCR<SUR> bit. If the CAN bus line is not
In suspend mode, the CAN controller is not active on the CAN bus line. That means neither error frames
If suspend mode is requested during the bus off recovery sequence execution, the CAN controller enters sus-
To restart the CAN controller, the <SUR> bit needs to be programmed to "0". After leaving the bus off
The CAN controller cancels suspend mode with a write of "0" to the <SUR> bit.
Sleep Mode
Suspend Mode
・ The message has been successfully transmitted.
・ The message has been successfully transmitted after an arbitration lost error.
・ The message has been successfully received after an arbitration lost error.
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TMPM364F10FG