TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 18

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

14. Serial Bus Interface (I2C/SIO)
x
13.4 Overview of SSP.................................................................................................................437
13.5 SSP operation......................................................................................................................441
13.6 Frame Format......................................................................................................................442
14.1 Configuration.......................................................................................................................450
14.2 Register................................................................................................................................451
14.3 I2C Bus Mode Data Format................................................................................................452
14.4 Control Registers in the I2C Bus Mode..............................................................................453
14.5 Control in the I2C Bus Mode..............................................................................................460
14.6 Data Transfer Procedure in the I2C Bus ModeI2C............................................................467
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.3.11
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.5.1
13.5.2
13.5.3
13.6.1
13.6.2
13.6.3
14.2.1
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
14.5.9
14.5.10
14.5.11
14.5.12
14.5.13
14.5.14
14.5.15
14.5.16
14.6.1
14.6.2
14.5.1.1
14.5.1.2
Register List...................................................................................................................................................................427
SSPCR0(Control register 0)..........................................................................................................................................428
SSPCR1(Control register1)...........................................................................................................................................429
SSPDR(Data register)....................................................................................................................................................430
SSPSR(Status register)..................................................................................................................................................431
SSPCPSR (Clock prescale register)..............................................................................................................................432
SSPIMSC (Interrupt enable/disable register)................................................................................................................433
SSPRIS (Pre-enable interrupt status register)...............................................................................................................434
SSPMIS (Post-enable interrupt status register)............................................................................................................435
Clock prescaler..............................................................................................................................................................437
Transmit FIFO...............................................................................................................................................................437
Receive FIFO.................................................................................................................................................................437
Interrupt generation logic..............................................................................................................................................438
DMA interface...............................................................................................................................................................440
Initial setting for SSP....................................................................................................................................................441
Enabling SSP.................................................................................................................................................................441
Clock ratios....................................................................................................................................................................441
SSI frame format...........................................................................................................................................................443
SPI frame format...........................................................................................................................................................444
Microwire frame format................................................................................................................................................446
Registers for each channel............................................................................................................................................451
SBIxCR0(Control register 0)........................................................................................................................................453
SBIxCR1(Control register 1)........................................................................................................................................454
SBIxCR2(Control register 2)........................................................................................................................................456
SBIxSR (Status Register)..............................................................................................................................................457
SBIxBR0(Serial bus interface baud rate register 0).....................................................................................................458
SBIxDBR (Serial bus interface data buffer register)....................................................................................................458
SBIxI2CAR (I2Cbus address register)..........................................................................................................................459
Serial Clock...................................................................................................................................................................460
Setting the Acknowledgement Mode............................................................................................................................461
Setting the Number of Bits per Transfer......................................................................................................................461
Slave Addressing and Address Recognition Mode......................................................................................................461
Operating mode.............................................................................................................................................................461
Configuring the SBI as a Transmitter or a Receiver....................................................................................................462
Configuring the SBI as a Master or a Slave.................................................................................................................462
Generating Start and Stop Conditions..........................................................................................................................462
Interrupt Service Request and Release.........................................................................................................................463
Device Initialization......................................................................................................................................................467
Generating the Start Condition and a Slave Address...................................................................................................467
SSPICR (Interrupt clear register)................................................................................................................................436
SSPDMACR (DMA control register).........................................................................................................................436
Arbitration Lost Detection Monitor............................................................................................................................463
Slave Address Match Detection Monitor....................................................................................................................465
General-call Detection Monitor...................................................................................................................................465
Last Received Bit Monitor..........................................................................................................................................465
Data Buffer Register (SBIxDBR)...............................................................................................................................465
Baud Rate Register (SBIxBR0)..................................................................................................................................466
Software Reset.............................................................................................................................................................466
Clock source
Clock Synchronization