AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 251

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.5.1.2
14.5.2
14.5.2.1
14.5.2.2
32099G–06/2011
Basic Operation
Changing the source clock
Prescaler
Counter operation
The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock
Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This
bit is set when the CEN bit in the CLOCK register is changed, and cleared when the CLOCK reg-
ister can be changed.
To change the clock:
When the AST is enabled, the 32-bit prescaler will increment on the rising edge of
CLK_AST_PRSC. The prescaler value cannot be read or written, but it can be reset by writing a
one to the Prescaler Clear bit in the Control Register (CR.PCLR).
The Prescaler Select field in the Control Register (CR.PSEL) selects the prescaler bit PSEL as
source clock for the counter (CLK_AST_CNT). This results in a counter frequency of:
where f
When enabled, the AST will increment on every 0-to-1 transition of the selected prescaler tap-
ping. When the Calender bit in the Control Register (CR.CAL) is zero, the counter operates in
counter mode. It will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to
0x00000000. This sets the status bit Overflow in the Status Register (SR.OVF). Optionally, the
counter can also be reset when an alarm occurs (see
also set the OVF bit.
The AST counter value can be read from or written to the Counter Value (CV) register. Note that
due to synchronization, continuous reading of the CV register with the lowest prescaler setting
will skip every third value. In addition, if CLK_AST_PRSC is as fast as, or faster than, the
CLK_AST, the prescaler value must be 3 or higher to be able to read the CV without skipping
values.
• Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write the selected value to CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a one to CLOCK.CEN to enable the clock, without changing the CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
PRSC
is the frequency of the internal prescaler clock CLK_AST_PRSC.
f
CNT
=
---------------------- -
2
PSEL
f
PRSC
+
1
Section 14.5.3.2 on page
AT32UC3L016/32/64
253. This will
251