AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 193
AT32UC3L064
Manufacturer Part Number
AT32UC3L064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L016.pdf
(843 pages)
4.AT32UC3L016.pdf
(110 pages)
Specifications of AT32UC3L064
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3L016 PDF datasheet #3
- AT32UC3L016 PDF datasheet #4
- Current page: 193 of 843
- Download datasheet (13Mb)
13.5.3.8
13.5.3.9
13.5.4
32099G–06/2011
Brown-Out Detection (BOD)
Accuracy
Interrupts
locks will not be lost. When the reference clock has restarted, the FINE tracking will quickly com-
pensate for any frequency drift during sleep.
There are mainly three factors that decide the accuracy of the f
obtain maximum accuracy when fine lock is acheived.
A interrupt can be generated on a zero-to-one transaction on DFLLnLOCKC, DFLLnLOCKF,
DFLLnLOCKA, DFLLnLOCKLOSTC, DFLLnLOCKLOSTF, DFLLnLOCKLOSTA, DFLLnRDY or
DFLLnRCS.
Rev: 1.0.1.0
The Brown-Out Detector monitors the VDDCORE supply pin and compares the supply voltage
to the brown-out detection level.
The BOD is disabled by default, and is enabled by writing to the BOD Control field (CTRL) in the
BOD Control Register (BOD). This field can also be updated by flash fuses.
The brown-out detection level is selected by writing to the BOD Level field (LEVEL) in BOD.
Please refer to Electrical Characteristics for parametric details.
If the BOD Control field (CTRL) in BOD is written to two and the supply voltage goes below the
detection level, the Brown-Out Detection bit (BODDET) in PCLKSR is set. This bit is cleared
when the supply voltage goes above the detection level. An interrupt can be generated on a zero
to one transition on PCLKSR.BODDET. If the BOD.CTRL field is written to one, a BOD reset will
be generated when the supply voltage goes below the detection level, resetting the device. Writ-
ing a one to the BOD Hysteresis bit (HYST) in BOD will add a hysteresis on the BOD detection
level.
Note that the BOD should be disabled before changing BOD.LEVEL, to avoid spurious reset or
interrupt. After enabling the BOD, the BOD output will be masked during one half of a RCSYS
clock cycle and two main clocks cycles to avoid false results.
When JTAG or aWire is enabled, the BOD reset and interrupt are masked.
The CTRL, HYST and LEVEL fields in the BOD Control Register are loaded from Flash Fuse
after a reset. It is still possible to override these values after reset by writing to the BOD Control
Register. Please refer to the Fuse setting chapter for more details about BOD fuses and how to
program the fuses.
If the Flash Calibration Done (FCD) bit in the BOD Control Register is zero at BOD reset then
the flash calibration will be redone and the BOD.FCD bit will be set before program execution
starts in the CPU. If the BOD.FCD is one then the BOD configuration will not be changed during
• FINE resolution: The frequency step between two FINE values. This is relatively smaller for
• Resolution of the measurement: If the resolution of the measured f
• The accuracy of the reference clock.
high output frequencies.
between CLK_DFLL frequency and CLK_DFLLIF_REF is small, then the DFLLIF might lock
at a frequency that is lower than the targeted frequency. It is recommended to use a
reference clock frequency of 32 KHz or lower to avoid this issue for low target frequencies.
AT32UC3L016/32/64
DFLL
DFLL
. These can be tuned to
is low, i.e. the ratio
193
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