AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet
AT32UC3L064
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AT32UC3L064 Summary of contents
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... Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADC) with Bits Resolution – Internal Temperature Sensor ® ® 32-bit AVR Microcontroller 2 C-compatible ® 32-bit AVR Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary 32099G–06/2011 ...
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Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module ® – Hardware Assisted Atmel AVR – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors • QTouch Library Support – Capacitive Touch Buttons, Sliders, and ...
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Description The Atmel AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 high-perfor- mance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and ...
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The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller (PWMA) provides 8-bit ...
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Overview 2.1 Block Diagram Figure 2- 32099G–06/2011 Block Diagram MCKO MDO[5..0] MSEO[1..0] EVTI_N NEXUS EVTO_N CLASS 2+ TCK JTAG OCD TDO INTERFACE TDI TMS DATAOUT aWire RESET_N M S/M SAU S CONFIGURATION HSB-PB BRIDGE B POWER MANAGER ...
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... Analog Comparators Capacitive Touch Module JTAG aWire Max Frequency Packages 32099G–06/2011 Configuration Summary AT32UC3L064 64KB 16KB Digital Frequency Locked Loop 40-150MHz (DFLL) Crystal Oscillator 3-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099G–06/2011 TQFP48/QFN48 Pinout ...
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Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099G–06/2011 TLLGA48 Pinout AT32UC3L016/32/64 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G P ...
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Table 3-1. GPIO Controller Function Multiplexing Normal 40 PA19 19 VDDIO I/O Normal 25 PA20 20 VDDIN I/O Normal I/O (TWI, 24 PA21 21 VDDIN 5V tolerant SMBus) Normal 9 PA22 22 VDDIO I/O Normal 6 PB00 32 VDDIO I/O ...
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Refer to the ties of the TWI, 5V Tolerant, and SMBUS pins. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last ...
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Table 3-4. Pin MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function ACAN3 - ACAN0 Negative inputs for comparators "A" ACAP3 - ACAP0 Positive inputs for comparators "A" ACBN3 - ...
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Table 3-7. Signal Descriptions List TMS Test Mode Select RESET_N Reset PWMA35 - PWMA0 PWMA channel waveforms PWMAOD35 - PWMA channel waveforms, open drain PWMAOD0 mode GCLK4 - GCLK0 Generic Clock Output RC32OUT RC32K output at startup XIN0 Crystal 0 ...
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Table 3-7. Signal Descriptions List Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data TXD Transmit Data Note: 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description ...
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I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up ...
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RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be ...
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Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...
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Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d 4.3.2.5 Unimplemented Instructions ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
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Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
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EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
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Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
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An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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... Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...
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Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE0400 0xFFFE0800 0xFFFF0000 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32099G–06/2011 Peripheral Name FLASHCDW Flash Controller - FLASHCDW HMATRIX HSB Matrix - ...
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Table 5-3. Peripheral Address Mapping 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being ...
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The following GPIO registers are mapped on the local bus: Table 5-4. Port 0 1 32099G–06/2011 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) ...
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Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3L has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is ...
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Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). ...
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Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.62-1.98V ...
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Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in use Shutdown mode. Figure 6-4. In ...
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Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise ...
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Peripheral DMA Controller (PDCA) Rev: 1.2.2.1 7.1 Features • Multiple channels • Generates transfers between memories and peripherals such as USART and SPI • Two address pointers/counters per channel allowing double buffering • Performance monitors to measure average and ...
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Block Diagram Figure 7-1. High Speed Bus Matrix Controller 7.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 7.4.1 Power Management If the CPU enters a sleep ...
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Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 7.5 Functional Description 7.5.1 Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of ...
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If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 7.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be ...
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Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest ...
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The registers can also be manually reset by writing a one to the Channel Reset bit in the PCON- TROL register (PCONTROL.CHnRES). The Performance Channel Read/Write Latency registers (PRLATn and PWLATn) are saturating when their maximum count value is reached. ...
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User Interface 7.7.1 Memory Map Overview Table 7-1. PDCA Register Memory Map Address Range 0x000 - 0x03F 0x040 - 0x07F ... (0x000 - 0x03F)+m*0x040 0x800-0x830 0x834 The channels are mapped as shown in ters, shown in 7.7.2 Channel Memory ...
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Performance Monitor Memory Map Table 7-3. PDCA Performance Monitor Registers Offset 0x800 Performance Control Register 0x804 Channel0 Read Data Cycles 0x808 Channel0 Read Stall Cycles 0x80C Channel0 Read Max Latency 0x810 Channel0 Write Data Cycles 0x814 Channel0 Write Stall ...
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Memory Address Register Name: MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the ...
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Peripheral Select Register Name: PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral ...
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Transfer Counter Register Name: TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 • TCV: Transfer Counter Value Number of data items to be transferred ...
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Memory Address Reload Register Name: MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will ...
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Transfer Counter Reload Register Name: TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 • TCRV: Transfer Counter Reload Value Reload value for the TCR ...
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Control Register Name: CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 • ECLR: Transfer Error Clear Writing a zero to ...
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Mode Register Name: MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 • RING: Ring Buffer 0:The Ring buffer functionality is ...
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Status Register Name: SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 • TEN: Transfer Enabled This bit is cleared when ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 • TERR: Transfer Error This bit is cleared ...
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Performance Control Register Name: PCONTROL Access Type: Read/Write Offset: 0x800 Reset Value: 0x00000000 • MON1CH: Performance Monitor Channel 1 • MON0CH: Performance Monitor ...
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Performance Channel 0 Read Data Cycles Name: PRDATA0 Access Type: Read-only Offset: 0x804 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Read Stall Cycles Name: PRSTALL0 Access Type: Read-only Offset: 0x808 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Read Max Latency Name: PRLAT0 Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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Performance Channel 0 Write Data Cycles Name: PWDATA0 Access Type: Read-only Offset: 0x810 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Write Stall Cycles Name: PWSTALL0 Access Type: Read-only Offset: 0x814 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Write Max Latency Name: PWLAT0 Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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Performance Channel 1 Read Data Cycles Name: PRDATA1 Access Type: Read-only Offset: 0x81C Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Read Stall Cycles Name: PRSTALL1 Access Type: Read-only Offset: 0x820 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Read Max Latency Name: PLATR1 Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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Performance Channel 1 Write Data Cycles Name: PWDATA1 Access Type: Read-only Offset: 0x828 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Write Stall Cycles Name: PWSTALL1 Access Type: Read-only Offset: 0x82C Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Write Max Latency Name: PWLAT1 Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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PDCA Version Register Name: VERSION Access Type: Read-only Offset: 0x834 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number ...
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Module Configuration The specific configuration for each PDCA instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man- ager chapter for details. Table 7-6. ...
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Table 7-9. PID 32099G–06/2011 Peripheral Identity Values Direction Peripheral Instance RX SPI RX TWIM0 RX TWIM1 RX TWIS0 RX TWIS1 RX ...
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Flash Controller (FLASHCDW) Rev: 1.0.2.0 8.1 Features • Controls on-chip flash memory • Supports 0 and 1 wait state bus access • Buffers reducing penalty of wait state in sequential code or loops • Allows interleaved burst reads for ...
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Debug Operation When an external debugger forces the CPU into debug mode, the FLASHCDW continues nor- mal operation. If the FLASHCDW is configured in a way that requires periodically serviced by the CPU through interrupts or ...
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The first word is output on the bus, and the other word is put into an internal buffer read to a sequential address performed ...
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Figure 8-1. 8.4.5 High Speed Read Mode The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable (HSEN) and High Speed ...
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Figure 8-2. 8.4.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result ...
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Figure 8-3. All locations are doubleword locations Internally, the flash memory stores data in 64-bit doublewords. Therefore, the native data size of the Page Buffer is also a 64-bit doubleword. All locations ...
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The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded ...
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After programming, the page can be locked to prevent miscellaneous write or erase sequences. Locking is performed on a per-region basis, so locking a region locks all pages inside the region. Additional protection is provided for the lowermost address space ...
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Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: At least one lock region is protected, or BOOTPROT is different from 0. The erase command has been aborted and ...
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Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions: Table 8-2. General- Purpose fuse number 15:0 16 19:17 21:20 22 32099G–06/2011 General-purpose Fuses with ...
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The BOOTPROT fuses protects the following address space for the Boot Loader: Table 8-3. BOOTPROT The SECURE fuses have the following functionality: Table 8-4. SECURE erase or ...
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The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that the 16 lowest general-purpose fuse bits can also be written/erased using the commands for locking/unlocking regions, see 8.7 Security Bit The security bit allows the ...
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User Interface Table 8-5. FLASHCDW Register Memory Map Offset 0x00 Flash Control Register 0x04 Flash Command Register 0x08 Flash Status Register 0x0C Flash Parameter Register 0x10 Flash Version Register 0x14 Flash General Purpose Fuse Register Hi 0x18 Flash General ...
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Flash Control Register Name: FCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 FWS • BRBUF: Branch Target Instruction Buffer Enable 0: The Branch ...
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Flash Command Register Name: FCMD Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to ...
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Table 8-6. Semantic of PAGEN field in different commands Command Program GP Fuse Byte Erase All GP Fuses Quick Page Read Write User Page Erase User Page Quick Page Read User Page High Speed Mode Enable High Speed Mode Disable ...
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Flash Status Register Name: FSR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 LOCK15 LOCK14 23 22 LOCK7 LOCK6 HSMODE • LOCKx: Lock Region x Lock Status 0: The corresponding ...
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Flash Parameter Register Name: FPR Access Type: Read-only Offset: 0x0C Reset Value • PSZ: Page Size The size of each flash page. ...
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FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 8-9. Flash Size FSZ Flash Size FSZ 0 4 Kbyte Kbyte ...
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Flash Version Register Name: FVR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number ...
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Flash General Purpose Fuse Register High Name: FGPFRHI Access Type: Read-only Offset: 0x14 Reset Value GPF63 GPF62 23 22 GPF55 GPF54 15 14 GPF47 GPF46 7 6 GPF39 GPF38 This register is only used in systems ...
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Flash General Purpose Fuse Register Low Name: FGPFRLO Access Type: Read-only Offset: 0x18 Reset Value GPF31 GPF30 23 22 GPF23 GPF22 15 14 GPF15 GPF14 7 6 GPF07 GPF06 • GPFxx: General Purpose Fuse xx 0: ...
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Fuse Settings The flash contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO). The Flash General Purpose Fuse Register High (FGPFRHI) is not used. In addition to the ...
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Flash General Purpose Fuse Register Low (FGPFRLO BODEN 23 22 BODLEVEL[0] UPROT • BODEN: Brown Out Detector Enable BODEN Description 00 BOD disabled 01 BOD enabled, BOD reset enabled 10 BOD enabled, BOD ...
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First Word of the User Page (Address 0x80800000 • WDTAUTO: WatchDog Timer Auto Enable at Startup 0: The WDT is automatically enabled at ...
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Second Word of the User Page (Address 0x80800004 • SSADRR: Secure State End Address for the RAM • SSADRF: Secure State End Address for the Flash 8.9.3.1 Default user page second ...
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... Flash size Number of pages Page size Table 8-11. Module Name FLASHCDW Table 8-12. Register FVR FPR 32099G–06/2011 Module Configuration AT32UC3L064 AT32UC3L032 64Kbytes 32Kbytes 256 128 256 bytes 256 bytes Module Clock Name Clock Name Description CLK_FLASHCDW_HSB Clock for the FLASHCDW HSB interface ...
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Secure Access Unit (SAU) Rev: 1.1.0.3 9.1 Features • Remaps registers in memory regions protected by the MPU to regions not protected by the MPU • Programmable physical address for each channel • Two modes of operation: Locked and ...
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Block Diagram Figure 9-1 some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory accesses are ...
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Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 9.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU ...
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Protecting SAU configuration registers In order to prevent the SAU configuration registers to be changed by malicious or runaway code, they should be protected by the MPU as soon as they have been configured. Maximum security is provided in ...
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Operation example Figure 9-2 als, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has ...
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Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits in SR were set (see The unlock operation was aborted. • ...
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User Interface The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base address. Table 9-1. SAU Configuration Register Memory Map Offset 0x00 0x04 0x08 Channel Enable Register High 0x0C Channel ...
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Control Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 BERRDIS • BERRDIS: Bus Error Response Disable Writing a zero to ...
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Configuration Register Name: CONFIG Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 • OPEN: Open Mode Enable Writing a zero to this bit disables open mode. Writing ...
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Channel Enable Register High Name: CERH Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is ...
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Channel Enable Register Low Name: CERL Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled. ...
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Status Register Name: SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000400 RTRADR MBERROR • IDLE This bit is cleared when a read or write ...
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CAU: Channel Access Unsuccessful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access was unsuccessful, i.e. an access was attempted to a locked or disabled channel. • ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 RTRADR MBERROR 0: The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has ...
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Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x24 Reset Value • CHANNELS: Number of channels implemented 32099G–06/2011 ...
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Version Register Name: VERSION Access Type: Write-only Offset: 0x28 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version ...
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Remap Target Register n Name: RTRn Access Type: Read/Write Offset: n*4 Reset Value: 0x00000000 • RTR: Remap Target Address for Channel n RTR[31:16] must have one of the following values, any ...
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Unlock Register Name: UR Access Type : Write-only Offset: 0xFC Reset Value: 0x00000000 • KEY: Unlock Key The correct key must be written in order to unlock a channel. ...
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Module Configuration The specific configuration for each SAU instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 9-3. Feature ...
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HSB Bus Matrix (HMATRIXB) Rev: 1.3.0.3 10.1 Features • User Interface on peripheral bus • Configurable number of masters (up to 16) • Configurable number of slaves (up to 16) • One decoder for each master • Programmable arbitration ...
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To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE ...
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Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix pro- vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst ...
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Other non privileged masters still get one latency cycle if they want to access the same slave. This technique ...
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User Interface Table 10-1. HMATRIX Register Memory Map Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration Register ...
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Table 10-1. HMATRIX Register Memory Map (Continued) Offset Register 0x008C Priority Register B for Slave 1 0x0090 Priority Register A for Slave 2 0x0094 Priority Register B for Slave 2 0x0098 Priority Register A for Slave 3 0x009C Priority Register ...
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Table 10-1. HMATRIX Register Memory Map (Continued) Offset Register 0x012C Special Function Register 7 0x0130 Special Function Register 8 0x0134 Special Function Register 9 0x0138 Special Function Register 10 0x013C Special Function Register 11 0x0140 Special Function Register 12 0x0144 ...
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Master Configuration Registers Name: MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type Table 10-2. ...
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Slave Configuration Registers Name: SCFG0...SCFG15 Access Type: Read/Write Offset: 0x40 - 0x7C Reset Value: 0x00000010 31 30 – – – – – – • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority ...
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Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 • MxPR: Master x Priority ...
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Priority Registers B For Slaves Name: PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 • MxPR: Master x Priority Fixed priority of ...
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Special Function Registers Name: SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field ...
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Module Configuration The specific configuration for each HMATRIX instance is listed in the following tables.The mod- ule bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 10-3. ...
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Figure 10-1. HMatrix Master / Slave Connections 32099G–06/2011 HMATRIX SLAVES 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 SAU 3 PDCA 4 AT32UC3L016/32/ 139 ...
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Interrupt Controller (INTC) Rev: 1.0.2.5 11.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • groups of interrupts with ...
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Figure 11-1. INTC Block Diagram NMIREQ IREQ63 IREQ34 IREQ33 IREQ32 IREQ31 IREQ2 IREQ1 IREQ0 11.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 11.4.1 Power Management If the ...
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Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, ...
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AT32UC3L016/32/64 143 ...
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User Interface Table 11-1. INTC Register Memory Map Offset Register 0x000 Interrupt Priority Register 0 0x004 Interrupt Priority Register 1 ... 0x0FC Interrupt Priority Register 63 0x100 Interrupt Request Register 0 0x104 Interrupt Request Register 1 ... 0x1FC Interrupt ...
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Interrupt Priority Registers Name: IPR0...IPR63 Access Type: Read/Write Offset: 0x000 - 0x0FC Reset Value: 0x00000000 31 30 INTLEVEL[1: • INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt ...
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Interrupt Request Registers Name: IRR0...IRR63 Access Type: Read-only Offset: 0x0FF - 0x1FC Reset Value: N IRR[32*x+31] IRR[32*x+30] IRR[32*x+29 IRR[32*x+23] IRR[32*x+22] IRR[32*x+21 IRR[32*x+15] IRR[32*x+14] IRR[32*x+13 IRR[32*x+7] IRR[32*x+6] IRR[32*x+5] • IRR: Interrupt Request ...
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Interrupt Cause Registers Name: ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N • CAUSE: Interrupt Group Causing Interrupt of Priority ...
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Module Configuration The specific configuration for each INTC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man- ager chapter for details. Table 11-2. ...
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Table 11-3. 32099G–06/2011 Interrupt Request Signal Map 0 Asynchronous Timer 1 Asynchronous Timer 10 2 Asynchronous Timer 3 Asynchronous Timer 0 External Interrupt Controller 1 External Interrupt Controller 11 2 External Interrupt Controller 3 External Interrupt Controller 12 0 External ...
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Table 11-3. 32099G–06/2011 Interrupt Request Signal Map 28 0 Analog Comparator Interface 29 0 Capacitive Touch Module 30 0 aWire AT32UC3L016/32/64 ACIFB CAT AW 150 ...
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Power Manager (PM) Rev: 4.1.1.4 12.1 Features • Generates clocks and resets for digital logic • On-the-fly frequency change of CPU, HSB and PBx clocks • Sleep modes allow simple disabling of logic clocks and clock sources • Module-level ...
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Block Diagram Figure 12-1. PM Block Diagram Main Clock Sources Reset Sources Power-On Detector External Reset Pin 12.4 I/O Lines Description Table 12-1. I/O Lines Description Name Description RESET_N Reset 12.5 Product Dependencies 12.5.1 Interrupt The PM interrupt line ...
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Functional Description 12.6.1 Synchronous Clocks The System RC Oscillator (RCSYS) and a selection of other clock sources can provide the source for the main clock, which is the origin for the synchronous CPU/HSB and PBx module clocks. For details ...
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Similarly, the PBx clocks can be divided by writing their respective Clock Select (PBxSEL) regis- ters. To ensure correct operation, the frequencies must never exceed the specified maximum frequency for each clock domain, and be selected so that f The ...
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The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not ...
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In Shutdown the only wake up sources are external reset, external wake-up pin or AST. See Section 12.6.4.3 on page Table 12-3. Index Notes: ™ 12.6.3.4 SleepWalking In all sleep modes where the ...
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The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com- plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary. When entering a sleep ...
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The 32KHz RC oscillator (RC32K) must be running and stable. This is done by As soon as the Shutdown sleep mode is entered, all CPU and peripherals are reset to ensure a consistent state. POR33 and RC32K are automatically ...
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The device contains a Power-On Detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device also possible to reset the device ...
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Depending on the reset source, when a Reset occurs, some parts of the device are not always reset. Only the Power On Reset (POR) will force a whole device reset. Refer to the table in the Module Configuration section at ...
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User Interface Table 12-7. PM Register Memory Map Offset 0x000 Main Clock Control 0x004 CPU Clock Select 0x008 HSB Clock Select 0x00C PBA Clock Select 0x010 PBB Clock Select 0x014 - 0x01C 0x020 0x024 0x028 0x02C 0x030- 0x03C 0x040 ...
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Main Clock Control Name: MCCTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 • MCSEL: Main Clock Select Table 12-8. Main clocks in ...
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CPU Clock Select Name: CPUSEL Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 CPUDIV - • CPUDIV, CPUSEL: CPU Division and Clock Select CPUDIV = ...
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HSB Clock Select Name: HSBSEL Access Type: Read Offset: 0x008 Reset Value: 0x00000000 HSBDIV - This register is read-only and its content is always equal ...
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PBx Clock Select Name: PBxSEL Access Type: Read/Write Offset: 0x008-0x00C Reset Value: 0x00000000 PBDIV - • PBDIV, PBSEL: PBx Division and Clock Select PBDIV = ...
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Clock Mask Name: CPUMASK/HSBMASK/PBAMASK/PBBMASK Access Type: Read/Write Offset: 0x020-0x02C Reset Value • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n ...
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Table 12-9. Maskable Module Clocks in AT32UC3L. Bit CPUMASK SYSTIMER 31:26 - Note ...
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Divided Clock Mask Name: PBADIVMASK Access Type: Read/Write Offset: 0x040 Reset Value: 0x0000007F • MASK: Clock Mask If bit n is written to zero, the ...
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Clock Failure Detector Control Register Name: CFDCTRL Access Type: Read/Write Offset: 0x054 Reset Value: 0x00000000 31 30 SFV - • SFV: Store Final Value 0: The register ...
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PM Unlock Register Name: UNLOCK Access Type: Write-Only Offset: 0x058 Reset Value: 0x00000000 unlock a write protected register, first write to the UNLOCK register with the ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C0 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0C4 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 The corresponding interrupt is cleared. 1: The corresponding interrupt ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0D0 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Status Register Name: SR Access Type: Read-only Offset: 0x0D4 Reset Value: 0x00000000 • AE: Access Error 0: No access error has occurred. 1: ...
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Peripheral Power Control Register Name: PPCR Access Type: Read/Write Offset: 0x004 Reset Value: 0x000001FA Table 12-11. Peripheral Power Control Bit Name 0 RSTPUN 1 FRC32 2 RSTTM 3 CATRCMASK 4 ACIFBCRCMASK ...
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CATRCMASK: CAT Request Clock Mask 0: CAT Request Clock is disabled 1: CAT Request Clock is enabled • ACIFBRCMASK: ACIFB Request Clock Mask 0: ACIFB Request Clock is disabled 1: ACIFB Request Clock is enabled • ADCIFBRCMASK: ADCIFB Request ...
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Reset Cause Name: RCAUSE Access Type: Read-only Offset: 0x180 Reset Value: Latest Reset Source SLEEP • AWIRE: AWIRE Reset The CPU was reset by ...
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Wake Cause Register Name: WCAUSE Access Type: Read-only Offset: 0x184 Reset Value: Latest Wake Source bit in this register is set on wake up caused by the peripheral referred to ...
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Asynchronous Wake Up Enable Register Name: AWEN Access Type: Read/Write Offset: 0x188 Reset Value: 0x00000000 Each bit in this register corresponds to an asynchronous wake up, according to 0: The corresponding ...
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Configuration Register Name: CONFIG Access Type: Read-Only Offset: 0x3F8 Reset Value HSBPEVC - This register shows the configuration of the PM. • HSBPEVC:HSB PEVC ...
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Version Register Name: VERSION Access Type: Read-Only Offset: 0x3FC Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version ...
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Module Configuration The specific configuration for each PM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the “Synchronous Clocks”, “Peripheral Clock Masking” and “Sleep ...
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System Control Interface (SCIF) Rev: 1.0.2.2 13.1 Features • Supports crystal oscillator 0.45-16MHz (OSC0) • Supports Digital Frequency Locked Loop 40-150MHz (DFLL) • Supports 32KHz ultra-low-power oscillator (OSC32K) • Supports 32kHz RC oscillator (RC32K) • Integrated low-power RC oscillator ...
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GPIO. When oscillators are used, the related pins are controlled directly by the SCIF, over- riding GPIO settings. RC32OUT will be outputted after reset, and can GPIO controller can assign this pin to other peripheral function after start-up. 13.4.2 ...
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The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCn Ready bit (OSCnRDY) in the Power and Clock Status Register (PCLKSR) is set when the oscillator is ...
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Internal oscillator with no external components • 40-150 MHz frequency in closed-loop mode • Can operate standalone as a high-frequency programmable oscillator in open loop mode • Can operate as an accurate frequency multiplier against a known frequency in ...
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Before reading the value in any of the DFLL configuration registers a one must be written to the Synchronization bit (SYNC) in the DFLLn Synchronization Register (DFLLnSYNC). The DFLL configuration registers are ready to be read when PCLKSR.DFLLnRDY is set. ...
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The locking of the frequency in closed-loop mode is divided into three stages. In the COARSE stage the control logic quickly finds the correct value for DFLLnCONF.COARSE and thereby sets the output frequency to a value close to the correct ...
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Figure 13-3. DFLL Locking in Closed-Loop CLK_DFLL is ready to be used when the DFLLn Synchronization Ready bit (DFLLnRDY) in PCLKSR is set after enabling the DFLL. However, the accuracy of the output frequency depends on which locks are set. ...
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Spread Spectrum Generator (SSG) When the DFLL is used as the main clock source for the device, the EMI radiated from the chip will be synchronous to f can provide a clock with the energy spread in ...
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When the reference clock has restarted, the FINE tracking will quickly com- pensate for any frequency drift during sleep. 13.5.3.8 Accuracy There are mainly three factors that decide the accuracy of the f obtain maximum ...
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BOD reset. To prevent unexpected writes to BOD due to software bugs, write access to this register is protected by a locking mechanism. For details please refer to the UNLOCK register description. The BOD is powered by VDDIO and ...
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RC Oscillator Calibration Register (RCCR). After a Power-On Reset (POR), the RCCR.CALIB field is loaded with a factory defined value stored in the Flash fuses. Please refer to the Fuse setting chapter for more details about ...
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Although it is not recommended to override default factory settings still possible to override these default values by writing to VREGCR.CALIB or altering the values for the VREGIFB flash fuses. If the Flash Calibration Done (FCD) bit in ...
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The SM33 can operate in continuous mode or in sampling mode. In sampling mode, the SM33 i s periodically enabled for a short period of time, just enough to make a a measurement and then disabled for a longer time ...
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The oscillator is automatically disabled in certain sleep modes to reduce power consumption, as described in the Power Manager chapter. 13.5.11 Backup Registers (BR) Rev: 1.0.0.1 Four 32-bit backup registers are available to store values when the chip is in ...
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Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in the SCIF Module Configuration section. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently ...
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Generic clock allocation The generic clocks are allocated to different functions as shown in the “Generic Clock Allocation” table in the SCIF Module Configuration section. 13.5.14 Interrupts The SCIF has 14 interrupt sources: • Access Error: – ...