AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 192

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.3.6
13.5.3.7
32099G–06/2011
Spread Spectrum Generator (SSG)
Wake from sleep modes
where
ratio.
When the DFLL is used as the main clock source for the device, the EMI radiated from the chip
will be synchronous to f
can provide a clock with the energy spread in the frequency domain. This is done by adding or
subtracting values from the FINE value. SSG is enabled by writing a one to the Enable bit (EN)
in the DFLLn Spread Spectrum Generator Control Register (DFLLnSSG).
A generic clock sets the rate at which the SSG changes the frequency of the DFLL clock to gen-
erate a spread spectrum (CLK_DFLLIF_DITHER). This is the same clock used by the dithering
mechanism. The frequency of this clock should be higher than f
can lock. Please refer to the Generic clocks section for details.
Optionally, the clock ticks can be qualified by a Pseudo Random Binary Sequence (PRBS) if the
PRBS bit in DFLLnSSG is one. This reduces the modulation effect of CLK_DFLLIF_DITHER fre-
quency onto f
The amplitude of the frequency variation can be selected by setting the SSG Amplitude field
(AMPLITUDE) in DFLLnSSG. If AMPLITUDE is zero the SSG will toggle on the LSB of the FINE
value. If AMPLITUDE is one the SSG will add the sequence {1,-1, 0} to FINE.
The step size of the SSG is selected by writing to the SSG Step Size field (STEPSIZE) in
DFLLnSSG. STEPSIZE equal to zero or one will result in a step size equal to one. If the step
size is set to n, the output value from the SSG will be incremented/decremented by n on every
tick of the source clock.
The Spread Spectrum Generator is available in both open and closed-loop mode.
When spread spectrum is enabled in closed-loop mode, and the AMPLITUDE is high, an over-
flow/underflow in FINE is more likely to occur.
Figure 13-4. Spread Spectrum Generator Block Diagram.
When waking up from a sleep mode where the DFLL has been turned off, and CLK_DFLL was
the main clock before going to sleep, the DFLL will be re-enabled and start running with the
same configuration as before it was stopped even if the reference clock is not available. The
2
CLK_DFLLIF_DITHER
NUMREF
DFLL
is the number of reference clock cycles the DFLLIF is using for calculating the
.
DFLL
. To provide better Electromagnetic Compatibility (EMC) the DFLLIF
Binary Sequence
Pseudorandom
error
=
RATIODIFF f
------------------------------------------------ -
2
PRBS
NUMREF
1
0
⋅
Spread Spectrum
AT32UC3L016/32/64
f
AMPLITUDE,
DFLL
⋅
STEPSIZE
Generator
REF
FINE
REF
to ensure that the DFLLIF
9
To DFLL
192