MT29F4G08ABBDAH4:D Micron Technology Inc, MT29F4G08ABBDAH4:D Datasheet - Page 26

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MT29F4G08ABBDAH4:D

Manufacturer Part Number
MT29F4G08ABBDAH4:D
Description
MICMT29F4G08ABBDAH4:D 4G SLC NAND FLASH
Manufacturer
Micron Technology Inc

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Figure 18: READ/BUSY# Open Drain
PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. J 9/11 EN
driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an
interrupt pin on the system controller.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing re-
quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10%
and 90% points on the R/B# waveform, the rise time is approximately two time con-
stants (TC).
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 23 (page 29).
The minimum value for Rp is determined by the output drive capability of the R/B# sig-
nal, the output voltage swing, and V
Where Σ
V
V
CC
SS
IL
is the sum of the input currents of all devices tied to the R/B# pin.
I
Rp =
OL
V
Device
CC
(MAX) - V
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
I
OL
T
26
C
R/B#
Open drain output
+ Σ
= R × C
OL
IL
Asynchronous Interface Bus Operation
CC
Rp
(MAX)
.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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