71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 72

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFM Details
The following occurs upon entering SFM.
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The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transactions that write two bytes to an even
address. The write transactions must contain a command byte of 0x00 which is the form that does not
create an MPU interrupt. Auto incrementing is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be 0x80 in SFM read transactions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is shown in the
SPI Transactions
71M6543F/H and 71M6543G/GH Data Sheet
disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is:
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2.5.13 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6543. It uses the
RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET pin
were pulled high, except that the I/O RAM bits are in the same state as after a wake-up from SLP or LCD
modes (see the I/O RAM description in
Four thousand, one hundred CK32 cycles (or 125 ms) after the WDT overflow, the MPU is launched from
program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see
WDT is disabled when the ICE_E pin is pulled high.
For details, see
72
First, write to SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM mode.
Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This write invokes SFM provided that the
previous write operation to SFMM met the requirements. Writing any other pattern to this register
does not invoke SFM. Additionally, any write operations to this register automatically reset the
previously written SFMM register values to zero.
The CE is disabled.
The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the
VBAT pin).
The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
Mass erase is invoked if specified in the SFMM (I/O RAM 0x2080) register (see Invoking SFM, above).
The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles.
All SPI read and write operations now refer to Flash instead of XRAM space.
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0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM.
0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes
will not be blocked and it is up to the user to guarantee that only previously unwritten
locations are written. This mode is not accessible when SPI secure mode is set.
SFM is not invoked if any other pattern is written to the SFMM register.
3.3.4 Watchdog Timer (WDT)
description on Page 69.SPI Transactions
© 2008–2011 Teridian Semiconductor Corporation
5.2
for a list of I/O RAM bit states after RESET and wake-up).
Reset.
3.4 Wake-Up
Behavior). The
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