71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 59

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71M6543F-IGT/F

Manufacturer Part Number
71M6543F-IGT/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet

Specifications of 71M6543F-IGT/F

Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
51
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-100
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in
Example: SEGDIO12 (pin 32 in
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured
as an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5
of LCD_SEG12.
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs.
internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0]. If
more than one input is connected to the same resource, the resources are combined using a logical OR.
v1.2
PORT_E.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pullup or pulldown resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See
Value in DIO_Rn[2:0]
Figure 16,
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
Table
0
1
2
3
4
5
Table
© 2008–2011 Teridian Semiconductor Corporation
48.
right), not source it from V3P3D (as shown in
Table
on page 139.
49.
48) is configured as a DIO output pin with a value of 1 (high) by
Resource Selected for SEGDIOn or PB Pin
None
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (INT0)
Low priority I/O interrupt (INT1)
71M6543F/H and 71M6543G/GH Data Sheet
Figure
Figure
12.
16, left). This is due
Table 48
lists the
59

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