71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 43

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in
addition to the interrupt 6, 4 and enable and flag bits (see
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 35)
v1.2
Group
EX_WPULSE
EX_XPULSE
EX_VPULSE
EX_YPULSE
by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in
EX_RTC1M
EX_RTC1S
EX_XFER
EX_RTCT
EX_EEX
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag is cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
0
1
2
3
4
5
EX_SPI
Name
EX0
EX1
EX2
EX3
EX4
EX5
EX6
Interrupt Enable
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
SFR A8[[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
Location
2700[0]
2700[1]
2700[2]
2700[4]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
© 2008–2011 Teridian Semiconductor Corporation
Table 34: Interrupt Priority Level Groups
Table 33: Interrupt Enable and Flag Bits
–
IE_WPULSE
IE_XPULSE
IE_YPULSE
IE_VPULSE
IE_RTC1M
IE_RTC1S
IE_XFER
IE_RTCT
IE_EEX
IE_SPI
Name
IEX2
IEX3
IEX4
IEX5
IEX6
IE0
IE1
Interrupt Flag
Serial channel 1 interrupt
Group Members
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[4]
SFR F8[3]
SFR 88[1]
SFR 88[3]
Location
Table 33: Interrupt Enable and Flag
Table
71M6543F/H and 71M6543G/GH Data Sheet
–
–
–
–
–
34.
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T interrupt (int 6)
SPI interrupt
EEPROM interrupt
CE_Xpulse interrupt (int 2)
CE_Ypulse interrupt (int 2)
CE_Wpulse interrupt (int 2)
CE_Vpulse interrupt (int 2)
Interrupt Description
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
–
Bits).
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