71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 54

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Refer to
RTC_P[16:0] and RTC_Q[1:0]. The 8-bit values loaded in to NV RAM must be scaled correctly to produce
4. Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM
71M6543F/H and 71M6543G/GH Data Sheet
limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal).
The 8-bit NV RAM content pointed to by the address is added as a 2’s complement value to 0x40000,
the nominal value of 4*RTC_P[16:0] + RTC_Q[1:0].
rate adjustments that are consistent with the equations given in
and RTC_Q[1:0]. Note that the sum of the looked-up 8-bit 2’s complement value and 0x40000 form a 19-
bit value, which is equal to 4*RTC_P[16:0] + RTC_Q[1:0], as shown in
Temperature Compensation is automatically loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after
each look-up and summation operation.
The 128 NV RAM locations are organized in 2’s complement format. As mentioned above, the
STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM addresses are
equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See
page
For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties
with respect to temperature, which is typically done once during initialization. Since the lookup table is
not directly addressable, the MPU uses the following procedure to load the NV RAM table:
1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
3. Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888).
5.
6. Repeat steps 3 through 5 until all data has been written to NV RAM.
of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] (I/O RAM 0x2887[6:0]) auto-increments every time LKP_RD or
LKP_WR is pulsed. It is also possible to perform random access of the NV RAM by writing a 0 to the
LKPAUTOI bit and loading the desired address into LKPADDR[6:0].
2.5.4.5 RTC Interrupts
The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC
and RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the
minutes and hours registers both equal their respective target counts as defined in . The alarm clock
interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See
interrupt section for the enable bits and flags for these interrupts.
The minute and hour target registers are listed in
54
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process
Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM).
55
for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
2.5.4.3 RTC Rate Control
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage area as ordinary battery-backed NV storage space using the procedure described
above to read and write NV RAM data. In this case, the OSC_COMP bit (I/O RAM 0x28A0[5]) is
reset to disable the automatic oscillator temperature compensation feature.
STEMP
10+S
>>2
8+S
Figure 13: Automatic Temperature Compensation
LIMIT
-256
© 2008–2011 Teridian Semiconductor Corporation
-64
-64
for information on the rate adjustments performed by registers
63
63
255
6+S
Table
ADDR
Look Up
45.
RAM
Q
2.5.5 71M6543 Temperature Sensor
2.5.4.3 RTC Rate Control
7+S
0x40000
19
Figure 13.
Σ
19
4*RTC_P+RTC_Q
The output of the
for RTC_P[16:0]
Table 33
on
in the
v1.2