71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 48

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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The 71M6543 also includes hardware to protect against unintentional Flash write and erase. To enable flash
write and erase operations, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field. The
key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the Flash erase and write operation is
inhibited by hardware. Proper operation of this security key requires that there be no firmware function that
writes ‘0010’ to FLSH_UNLOCK[3:0]. The key should be written by the external SPI master, in the case of
SPI flash programming (SFM mode), or through the ICE interface in the case of ICE flash programming.
When a boot loader is used, the key should be sent to the boot load code which then writes it to
71M6543F/H and 71M6543G/GH Data Sheet
The page erase sequence is:
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Bank-Switching in the 71M6543G/GH
The 128 KB program memory in the 71M6543G/GH consists of a fixed lower bank of 32 KB, addressable
at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O
RAM register FL_BANK[1:0] (SFR 0xB6[1:0]) is used to switch four memory banks of 32 KB each into the
address range from 0x8000 to 0xFFFF. Note that when FL_BANK[1:0] (SFR 0xB6[1:0]) = 0, the upper
bank is the same as the lower bank.
In the 71M6543G/GH, the address that the FLSH_PGADR[6:0] (SFR 0xB7[7:1]) points to in the program
address space can reference different flash memory locations, depending on the setting of the
FL_BANK[1:0] (SFR 0xB6[1:0]) bits. The CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) field on the 71M6543G/GH
on the other hand, points directly to a location in the flash memory are not affected by the FL_BANK[1:0]
(SFR 0xB6[1:0]) bits
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE
operations, such as reading via the SPI or ICE port, are blocked. This guarantees the security of the user’s
MPU and CE program code. Security is enabled by MPU code that is executed in a 64 CKMPU cycle
pre-boot interval before the primary boot sequence begins. Once security is enabled, the only way to
disable it is to perform a global erase of the flash, followed by a chip reset.
The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU.
Upon completion of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE (SFR 0xB2[6]), is reset whenever the chip is reset. Hardware associated
with the bit allows only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security
feature but may not reset it. Once SECURE is set, the pre-boot and CE code are protected from erasure,
and no external read of program code is possible.
Specifically, when the SECURE bit is set, the following applies:
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Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94).
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
Write operations to page zero, whether by MPU or ICE are inhibited.
Table 40: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH
FL_BANK[1:0]
71M6543G/GH
00
01
10
11
© 2008–2011 Teridian Semiconductor Corporation
Address Range for Lower
Bank (0x0000-0x7FFF)
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
Address Range for Upper
Bank (0x8000-0xFFFF)
0x18000-0x1FFFF
0x10000-0x17FFF
0x8000-0xFFFF
0x0000-0x7FFF
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