71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 105

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

v1.2
Name
CHOP_E[1:0]
CHOPR[1:0]
DIFF0_E
DIFF2_E
DIFF4_E
DIFF6_E
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
SFR B0[7:4]
SFR A0[7:4]
SFR B0[3:0]
SFR A0[3:0]
SFR 90[3:0]
SFR 90[7:4]
SFR 80[7:4]
SFR 80[3:0]
Location Rst Wk Dir
2106[3:2]
2709[7:6] 00 00 R/W
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
210C[4]
210C[5]
210C[6]
210C[7]
F
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
F
F
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Chop enable for the reference bandgap circuit. The value of CHOP changes on the
rising edge of the internal MUXSYNC signal according to the value in CHOP_E[1:0]:
1
The CHOP settings for the remote sensor.
00 = Auto chop. Change every MUX frame.
01 = Positive
10 = Negative
11 = Auto chop (same as 00)
Enables IADC0-IADC1 differential configuration.
Enables IADC2-IADC3 differential configuration.
Enables IADC4-IADC5 differential configuration.
Enables IADC6-IADC7 differential configuration.
Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources. If more
than one input is connected to the same resource, the MULTIPLE column below specifies
how they are combined.
The value on the first 16 DIO pins. Pins configured as LCD read zero. When written,
changes data on pins configured as outputs. Pins configured as LCD or input ignore
writes. Note that the data for DIO pins above 15 is set by SEGDIOx[0].
Programs the direction of the first 16 DIO pins. 1 indicates output. Ignored if the pin is
not configured as I/O. See DIO_PV and DIO_PW for special option for DIO0 and DIO1
outputs. See DIO_EEX[1:0] for special option for SEGDIO2 and SEGDIO3. Note that
the direction of DIO pins above 15 is set by SEGDIOx[1]. See PORT_E to avoid power-
up spikes.
00 = toggle
except at the mux sync edge at the end of an accumulation interval.
DIO_Rx
0
1
2
3
4
5
Resource
NONE
Reserved
T0 (Timer0 clock or gate)
T1 (Timer1 clock or gate)
IO interrupt (int0)
IO interrupt (int1)
1
01 = positive
10 = reversed
71M6543F/H and 71M6543G/GH Data Sheet
11 = toggle
MULTIPLE
OR
OR
OR
OR
OR
–
105