71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 130

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

71M6543F/H and 71M6543G/GH Data Sheet
5.4.10 CE Calibration Parameters
Table 87
130
Note:
The current sensor inputs are not assigned to the A, B and C phases in a fixed manner. The
assignments of phases A, B and C depends on how the IADC0-1, IADC2-3, IADC4-5, IADC6-7 current
sensing inputs are connected in the meter design. The CE code must be aware of these connections.
See
assigned to voltage phases VA, VB and VC in a fixed manner, respectively.
The CE addresses listed in this table are assigned to phases A, B and C as indicated by their names.
Address
0x10
0x11
0x13
0x14
0x16
0x17
0x19
0x12
0x15
0x18
0x12
0x15
0x18
CE
Figure 31
lists the parameters that are typically entered to effect calibration of meter accuracy.
DLYADJ_C
DLYADJ_A
DLYADJ_B
PHADJ_A
PHADJ_B
PHADJ_C
CAL_VA
CAL_VB
CAL_VC
CAL_IC
CAL_ID
CAL_IA
CAL_IB
and
Name
Figure 32
© 2008–2011 Teridian Semiconductor Corporation
Defau
16384
16384
16384
16384
16384
16384
16384
lt
0
0
0
0
0
0
for typical meter configurations. VADC8, VADC9 and VADC10 are
Table 87: CE Calibration Parameters
These constants control the gain of their respective channels. The
nominal value for each parameter is 2
channel is directly proportional to its CAL parameter. Thus, if the
gain of a channel is 1% low, CAL should be increased by 1%.
These constants control the CT phase compensation. No
compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. The range is ± 2
is desired to delay the current by the angle Φ, the equations are:
The shunt delay compensation is obtained using the equation
provided below:
where:
The table below provides the value of A for each channel:
DLYADJ
PHADJ
PHADJ
_
X
_
_
=
X
X
∆
=
=
deg
2
2
rees
20
D YADJ_A
20
DLYADJ_B
DLYADJ_C
(
Channel
. 0
f
1
�� = 2��
s
. 0
+
1430
f is the mains frequency
is the sampling frequency
1714
0
1 .
. 0
. 0
∆
0206
029615
−
deg
2
Description
−
. 0
+ 4�������� �
b
rees
. 0
01226
a
= A
⋅
)
0168
2
TAN
=
14
TAN
2
360
2
2
⋅
π
A
Φ
+
⋅
TAN
TAN
14
Φ
1
a
2����
Value of A
(decimal)
��
2
= 16384. The gain of each
��
13840
11693
cos
Φ
9359
Φ
� + 2
2
at 50Hz

 

at 60Hz
2
π
f
s
f
c
sin

 

+

 

2
2
ab
π
f
s
f
cos
15

 


 

– 1. If it
2
π
f
s
f

 

+
v1.2
b