71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 21

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as
controlled by CROSS (an internal signal), in the A position, the output voltage is:
With all switches set to the B position by applying the inverted CROSS signal, the output voltage is:
Thus, when CROSS is toggled, e.g., after each multiplexer cycle, the offset alternately appears on the
output as positive and negative, which results in the offset effectively being eliminated, regardless of its
polarity or magnitude.
When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall
polarity of that amplifier gain; it inverts its input offset. By alternately reversing the connection, the amplifier’s
offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage
reference. The CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field controls the behavior of CROSS. On the
first CK32 rising edge after the last multiplexer state of its sequence, the multiplexer waits one additional
CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS is updated
according to the CHOP_E[1:0] field. The extra CK32 cycle allows time for the chopped VREF to settle.
During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates a pass through the CE
program sequence.
CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0]
= 01, CROSS is held low. In the reverse state, CHOP_E[1:0] = 10, CROSS is held high. The two
automatic toggling states are selected by setting CHOP_E=11 or CHOP_E=00.
Figure 7
first interval, CROSS is high, at the end of the second interval, CROSS is low. Operation with
CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU.
In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer
cycle in an accumulation interval.
v1.2
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
shows CROSS over two accumulation intervals when CHOP_E[1:0] = 00: At the end of the
V
V
inp
inn
Figure 6: General Topology of a Chopped Amplifier
CROSS
© 2008–2011 Teridian Semiconductor Corporation
Figure 7: CROSS Signal with CHOP_E = 00
A
B
A
B
+
-
G
71M6543F/H and 71M6543G/GH Data Sheet
A
B
B
A
V
V
outp
outn
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