ADSP-21364BSWZ-1AA Analog Devices Inc, ADSP-21364BSWZ-1AA Datasheet - Page 40

• Manufacturer Part Number: ADSP-21364BSWZ-1AA
• Description: IC DSP 32BIT 333MHZ EPAD 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21364BSWZ-1AA

• Interface: DAI, SPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
• Frequency: 333MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial, SPI
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case: RoHS Compliant
• No. Of Bits: 32 / 40
• Rohs Compliant: Yes
• Package: 144LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 333 MHz
• Ram Size: 384 KB
• Device Million Instructions Per Second: 333 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Master
The processor contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in
Table 39. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
SSPIDM
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
DDSPIDM
HDSPIDM
SDSCIM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2)
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
FLAG3–0
(CP = 0)
(CP = 1)
SPICLK
SPICLK
(INPUT)
(INPUT)
MOSI
MISO
MOSI
MISO
Table 39
t
SSPIDM
and
t
SDSCIM
Table 40
MSB VALID
t
HSPIDM
applies to both.
t
t
SPICHM
SPICLM
MSB
VALID
MSB
t
Rev. G | Page 40 of 56 | March 2011
SSPIDM
t
t
MSB
SPICLM
SPICHM
t
DDSPIDM
t
Figure 34. SPI Master Timing
HSPIDM
t
DDSPIDM
t
HDSPIDM
LSB VALID
t
SPICLKM
Min
5.2
8.2
2
8 × t
4 × t
4 × t
4 × t
4 × t
4 × t
4 × t
4 × t
K and B Grade
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
LSB
LSB VALID
– 2.5
– 2.5
t
– 2
– 2
– 2
– 2
– 2
– 1
HDSPIDM
Max
3.0
8.0
t
SSPIDM
t
HDSM
t
HSPIDM
Min
6.2
9.5
2
8 × t
4 × t
4 × t
4 × t
4 × t
4 × t
4 × t
4 × t
LSB
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
t
Y Grade
SPITDM
– 2
– 2
– 2
– 2
– 3.0
– 3.0
– 2
– 1
Max
3.0
9.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns