ADSP-21364BSWZ-1AA Analog Devices Inc, ADSP-21364BSWZ-1AA Datasheet
ADSP-21364BSWZ-1AA
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ADSP-21364BSWZ-1AA Summary of contents
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... On-chip memory—3M bits of on-chip SRAM Code compatible with all other members of the SHARC family The ADSP-2136x processors are available with up to 333 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF trans- ceiver, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, and more ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ............................................................... 1 Dedicated Audio Components .................................... 1 Revision History ...................................................... 2 General Description ................................................. 3 SHARC Family Core Architecture ............................ 4 Family Peripheral Architecture ................................ 6 I/O Processor Features ........................................... 8 System Design ...................................................... 8 Development Tools ............................................... 9 Additional Information ........................................ 10 Related Signal Chains .......................................... 10 Pin Function Descriptions ....................................... 11 Specifications ........................................................ 14 Operating Conditions .......................................... 14 Electrical Characteristics ....................................... 14 REVISION HISTORY 3/11—Rev Rev. G Revised S/PDIF Transmitter Input Data Timing ...
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... Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. The diagram ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARC FAMILY CORE ARCHITECTURE The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. ...
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... These 10-port, 32-register (16 primary, 16 secondary) files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and inter- nal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0– ...
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... The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2136x SPI- compatible peripheral implementation also features program- mable baud rate, clock phase, and polarities. The SPI- compatible port uses open drain drivers to support a multimas- ter configuration and to avoid data contention ...
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... Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. The S/PDIF and SRC are not available on the ADSP-21363 models. Input Data Port (IDP) The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs ...
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... SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port (PP). See Table 4. Table 4. DMA Channels Peripheral ADSP-2136x SPORTs 12 IDP/PDAP 8 SPI 2 MTM/DTCP ...
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... Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2136x processors. The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy-to-use assembler (based on an algebraic syn- ...
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... This data sheet provides a general overview of the processor’s architecture and functionality. For detailed informa- tion on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference. RELATED SIGNAL CHAINS ...
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... ADDR23–8; ALE is used in conjunction with an external latch to retain the values of the ADDR23–8. For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x SHARC Processor Hardware Reference. Parallel Port Read Enable asserted low whenever the processor reads 8-bit or 16- bit data from an external memory device. When AD15– ...
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... SPIDS signal on the SPI slave device. SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the processor’s JTAG emulators target board connector only. EMU has a 22.5 kΩ ...
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... Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI. 7 Typical internal current data reflects nominal operating conditions. 8 See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information. 9 Characterized, but not tested. 10 Applies to all signal pins. ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE INFORMATION The information presented in Figure 4 the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Page 54. ADSP-2136x tppZ-cc vvvvvv.x n.n #yyww country_of_origin Figure 4. Typical Package Brand Table 7. Package Brand Information Brand Key Field Description t Temperature Range ...
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... THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN. Note the definitions of the clock periods that are a function of VCO CLKIN and the appropriate ratio control shown in of the timing specifications for the ADSP-2136x peripherals are defined in relation to t tion for each peripheral’s timing information. Table 9. Clock Periods ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing The timing requirements for processor startup are given in Table 10. Note that during power-up, when the V supply comes up after leakage current of the order of DDEXT Table 10. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V ...
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... Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation Rev Page March 2011 1 2 333 MHz Min Max 1 18 100 1 7 3.0 10 200 800 –250 +250 . t CKJ ADSP-2136x R1 XTAL CLKIN 22pF 22pF Y1 24.576MHz R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS. *TYPICAL VALUES Unit MHz ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Table 12. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable V and CLKIN (not including start-up time of external clock oscillator) ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Table 14. Core Timer Parameter Switching Characteristic t TMREXP Pulse Width WCTIM FLAG3 (TMREXP) Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. ...
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... PCLK 4.5 3 2.5 10 2.5 + (2.5 × (2.5 × t PCGIP 2.5 + ((2 – PH) × ((2 – PH) × t PCGIP 2 × t – 1 PCGIP ADSP-2136x SHARC Processor Hardware Reference t t STRIG HTRIG t PCGIP t DPCGIO t t DTRIGCLK DPCGIO t DTRIGFS Figure 15. Precision Clock Generator (Direct Pin Routing) Rev Page March 2011 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 6 on Page 11 for more information on flag use. Table 19. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the processor is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements t AD7–0 Data Setup Before RD High DRS t AD7–0 Data Hold After RD High ...
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... ALE ALEW ADAS AD15–0 VALID ADDRESS NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE. K and B Grade Min Max 3 × t – 2.0 PCLK t – 2.5 PCLK 2 × ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the processor is accessing external memory space. Table 22. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW 1 t AD15–0 Address Setup Before ALE Deasserted ...
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... ALEW ADAS AD15–0 VALID ADDRESS NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE. K and B Grade Min 2 × t – 2.0 PCLK t – 2.5 PCLK 2 × ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (FS) delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Table 24. Serial Ports—External Clock ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW DAI_P20–1 (SCLK) t DFSIR t t HOFSIR SFSI DAI_P20–1 (FRAME SYNC) t SDRI DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 26. Serial Ports—External Late Frame Sync Parameter Switching Characteristics 1 t Data Delay from Late External Transmit Frame Sync DDTLFSE or External Receive FS with MCE = 1, MFD = Data Enable for MCE = 1, MFD = 0 DDTENFS 1 The t and t parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0. ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 27. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. DRIVE EDGE DAI_P20–1 (SCLK, EXT) DAI_P20– ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Input Data Port (IDP) The timing requirements for the IDP are given in signals are routed to the DAI_P20–1 pins using the SRU. There- fore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. IDP Parameter Timing Requirements ...
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... The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, refer to the ADSP-2136x SHARC Processor Hardware Reference, the chapter “Input Data Port.” Table 29. Parallel Data Acquisition Port (PDAP) Parameter ...
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... The SRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 31 are valid at the DAI_P20–1 pins. This feature is not available on the ADSP-21363 models. Table 31. SRC, Serial Input Port Parameter Timing Requirements ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and delay Table 32. SRC, Serial Output Port ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 29 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 2 Figure 30 shows the default I S-justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. 2 Table 34. S/PDIF Transmitter I ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 36. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 36. S/PDIF Transmitter Input Data Timing ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. This feature is not available on the ADSP-21363 processors. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode) ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The processor contains two SPI ports. The primary has dedi- cated pins and the secondary is available through the DAI. The timing provided in Table 39 and Table 40 Table 39. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements ...
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... SPIDS Assertion to Data Out Valid (CPHASE = 0) DSOV 1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. K and B Grade Min 4 × ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPIDS (INPUT) t SPICHS SPICLK ( (INPUT) t SDSCO SPICLK ( (INPUT) t DSOE MISO (OUTPUT) t CPHASE = 1 SSPIDS MOSI (INPUT) MISO (OUTPUT) t DSOV CPHASE = 0 MOSI (INPUT) t SPICLS t SPICLS t SPICHS t DDSPIDS MSB MSB VALID t DDSPIDS MSB t SSPIDS MSB VALID Figure 35. SPI Slave Timing Rev Page March 2011 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 JTAG Test Access Port and Emulation Table 41. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK High ...
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... SWEEP (V ) VOLTAGE (V) DDEXT Figure 37. ADSP-2136x Typical Drive TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 12 on Page 19 through Table 41 on Page output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage ...
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... JT is the typical value from Table 42 through P = power dissipation. See Estimating Power for the D ADSP-21362 SHARC Processors (EE-277) for more information. Values of θ are provided for package comparison and PCB JA design considerations. Values of θ design considerations when an exposed pad is required. Note ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 144-LEAD LQFP_EP PIN CONFIGURATIONS The following table shows the processor’s pin names and, when applicable, their default function after reset in parentheses. Table 45. LQFP_EP Pin Assignments Pin Name Pin No. Pin Name DDINT DDINT CLK_CFG0 2 GND CLK_CFG1 3 RD BOOT_CFG0 4 ALE BOOT_CFG1 ...
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... LQFP_EP lead configuration. LEAD 1 INDICATOR ADSP-2136x 144-LEAD LQFP_EP BOTTOM VIEW LEAD 144 LEAD 109 LEAD 1 ADSP-2136x 144-LEAD LQFP_EP TOP VIEW LEAD 36 LEAD 37 LEAD 72 Figure 43. 144-Lead LQFP_EP Lead Configuration (Top View) LEAD 109 LEAD 144 LEAD 108 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the processor’s ball names and, when applicable, their default function after reset in parentheses. Table 46. BGA Pin Assignments Ball Name Ball No. Ball Name CLK_CFG0 A01 CLK_CFG1 XTAL A02 GND TMS A03 V DDEXT ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 46. BGA Pin Assignments (Continued) Ball Name Ball No. Ball Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) J14 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 KEY V DDINT GND V A DDEXT VSS Figure 45. BGA Pin Assignments (Bottom View, Summary VDD I/O SIGNALS Rev Page March 2011 KEY V A DDINT VDD GND V A I/O SIGNALS DDEXT VSS Figure 46. BGA Pin Assignments (Top View, Summary ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE DIMENSIONS The processor is available in 136-ball BGA and 144-lead exposed pad (LQFP_EP) packages. 1.60 MAX 0.75 0.60 0.45 SEATING PLANE 1.45 1.40 0.20 1.35 0.09 7° 0.15 3.5° 0.05 0.08 0° COPLANARITY VIEW A ROTATED 90° CCW Figure 47. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] 22 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 1.70 MAX SURFACE-MOUNT DESIGN Table 47 is provided as an aid to PCB design. For industry stan- dard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 47. BGA Data for Use with Surface-Mount Design Package 136-Ball CSP_BGA (BC-136) 12 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 AUTOMOTIVE PRODUCTS Some ADSP-2136x models are available for automotive applica- tions with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. Table 48. Automotive Products Model Notes 2 AD21362WBBCZ1xx 2 AD21362WBSWZ1xx 2 AD21362WYSWZ2xx AD21363WBBCZ1xx AD21363WBSWZ1xx AD21363WYSWZ2xx ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ORDERING GUIDE 1 Model Notes 3 ADSP-21362BBCZ-1AA 3 ADSP-21362BSWZ-1AA 3 ADSP-21362YSWZ-2AA ADSP-21363KBC-1AA ADSP-21363KBCZ-1AA ADSP-21363KSWZ-1AA ADSP-21363BBC-1AA ADSP-21363BBCZ-1AA ADSP-21363BSWZ-1AA 4 ADSP-21363YSWZ-2AA ADSP-21364KBC-1AA ADSP-21364KBCZ-1AA ADSP-21364KSWZ-1AA ADSP-21364BBC–1AA ADSP-21364BBCZ-1AA ADSP-21364BSWZ-1AA ADSP-21364YSWZ-2AA ADSP-21365BBCZ-1AA ADSP-21365BSWZ-1AA ADSP-21365YSWZ-2AA ADSP-21365YSWZ-2CA 4, 5 ADSP-21366KBC-1AA ADSP-21366KBCZ-1AR 4, 5 ADSP-21366KBCZ-1AA 4, 5 ADSP-21366KSWZ-1AA 4, 5 ADSP-21366BBC–1AA 4, 5 ADSP-21366BBCZ-1AA 4, 5 ADSP-21366BSWZ-1AA ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev Page March 2011 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06359-0-3/11(G) Rev Page March 2011 ...