ADSP-21364BSWZ-1AA Analog Devices Inc, ADSP-21364BSWZ-1AA Datasheet - Page 22

• Manufacturer Part Number: ADSP-21364BSWZ-1AA
• Description: IC DSP 32BIT 333MHZ EPAD 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21364BSWZ-1AA

• Interface: DAI, SPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
• Frequency: 333MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial, SPI
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case: RoHS Compliant
• No. Of Bits: 32 / 40
• Rohs Compliant: Yes
• Package: 144LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 333 MHz
• Ram Size: 384 KB
• Device Million Instructions Per Second: 333 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 18. Precision Clock Generator (Direct Pin Routing)
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
D = FSxDIV, PH = FSxPHASE. For more information, refer to the
ators” chapter.
In normal mode, t
PCGIP
STRIG
HTRIG
DPCGIO
DTRIGCLK
DTRIGFS
PCGOP
1
Input Clock Period
PCG Trigger Setup Before Falling
Edge of PCG Input Clock
PCG Trigger Hold After Falling
Edge of PCG Input Clock
PCG Output Clock and Frame Sync
Active Edge Delay After PCG Input
Clock
PCG Output Clock Delay After PCG
Trigger
PCG Frame Sync Delay After PCG
Trigger
Output Clock Period
PCGOP
(min) = 2 × t
PCG_CLKx_O
PCG_TRIGx_I
PCG_EXTx_I
PCG_FSx_O
PCGIP
DAI_Pm
(CLKIN)
DAI_Pn
DAI_Py
DAI_Pz
.
t
STRIG
Figure 15. Precision Clock Generator (Direct Pin Routing)
Min
t
4.5
3
2.5
2.5 + (2.5 × t
2.5 + ((2.5 + D – PH) × t
2 × t
PCLK
PCGIP
Rev. G | Page 22 of 56 | March 2011
× 4
t
t
DPCGIO
t
DTRIGCLK
– 1
HTRIG
PCGIP
t
DTRIGFS
ADSP-2136x SHARC Processor Hardware Reference
)
K and B Grade
PCGIP
t
DPCGIO
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
) 10 + ((2.5 + D – PH) × t
t
PCGIP
Max
10
10 + (2.5 × t
PCGIP
)
t
PCGOP
PCGIP
) 12 + ((2.5 + D – PH) × t
Max
10
12 + (2.5 × t
, “Precision Clock Gener-
Y Grade
PCGIP
)
PCGIP
) ns
Unit
ns
ns
ns
ns
ns
ns