ADSP-21364BSWZ-1AA Analog Devices Inc, ADSP-21364BSWZ-1AA Datasheet - Page 32

IC DSP 32BIT 333MHZ EPAD 144LQFP

ADSP-21364BSWZ-1AA

Manufacturer Part Number
ADSP-21364BSWZ-1AA
Description
IC DSP 32BIT 333MHZ EPAD 144LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21364BSWZ-1AA

Interface
DAI, SPI
Clock Rate
333MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
384kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
Frequency
333MHz
Supply Voltage
1.2V
Embedded Interface Type
Serial, SPI
Supply Voltage Range
1.14V To 1.26V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case
RoHS Compliant
No. Of Bits
32 / 40
Rohs Compliant
Yes
Package
144LQFP EP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
333 MHz
Ram Size
384 KB
Device Million Instructions Per Second
333 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21364BSWZ-1AA
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Input Data Port (IDP)
The timing requirements for the IDP are given in
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 28. IDP
1
Parameter
Timing Requirements
t
t
t
t
t
t
The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Clock Rising Edge
Frame Sync Hold After Clock Rising Edge
Data Setup Before Clock Rising Edge
Data Hold After Clock Rising Edge
Clock Width
Clock Period
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
Table
Rev. G | Page 32 of 56 | March 2011
28. IDP
Figure 24. IDP Master Timing
t
IPDCLKW
t
SISFS
SAMPLE EDGE
t
SISD
t
t
SIHFS
SIHD
t
IPDCLK
Min
3
3
3
3
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Unit
ns
ns
ns
ns
ns
ns

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