ADSP-21364BSWZ-1AA Analog Devices Inc, ADSP-21364BSWZ-1AA Datasheet - Page 39

IC DSP 32BIT 333MHZ EPAD 144LQFP

ADSP-21364BSWZ-1AA

Manufacturer Part Number
ADSP-21364BSWZ-1AA
Description
IC DSP 32BIT 333MHZ EPAD 144LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21364BSWZ-1AA

Interface
DAI, SPI
Clock Rate
333MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
384kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
Frequency
333MHz
Supply Voltage
1.2V
Embedded Interface Type
Serial, SPI
Supply Voltage Range
1.14V To 1.26V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case
RoHS Compliant
No. Of Bits
32 / 40
Rohs Compliant
Yes
Package
144LQFP EP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
333 MHz
Ram Size
384 KB
Device Million Instructions Per Second
333 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21364BSWZ-1AA
Manufacturer:
Analog Devices Inc
Quantity:
10 000
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver. This feature is not available on the
ADSP-21363 processors.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)
1
Parameter
Switching Characteristics
t
t
t
t
t
Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Frame Sync Delay After Serial Clock
Frame Sync Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
(DATA CHANNEL
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
A/B)
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
DRIVE EDGE
Rev. G | Page 39 of 56 | March 2011
t
t
HOFSI
HDTI
t
t
DFSI
DDTI
t
SCLKIW
Min
–2
–2
38
SAMPLE EDGE
Max
5
5
Unit
ns
ns
ns
ns
ns

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