ADSP-21364BSWZ-1AA Analog Devices Inc, ADSP-21364BSWZ-1AA Datasheet - Page 37

IC DSP 32BIT 333MHZ EPAD 144LQFP

ADSP-21364BSWZ-1AA

Manufacturer Part Number
ADSP-21364BSWZ-1AA
Description
IC DSP 32BIT 333MHZ EPAD 144LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21364BSWZ-1AA

Interface
DAI, SPI
Clock Rate
333MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
384kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
Frequency
333MHz
Supply Voltage
1.2V
Embedded Interface Type
Serial, SPI
Supply Voltage Range
1.14V To 1.26V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case
RoHS Compliant
No. Of Bits
32 / 40
Rohs Compliant
Yes
Package
144LQFP EP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
333 MHz
Ram Size
384 KB
Device Million Instructions Per Second
333 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21364BSWZ-1AA
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Figure 30
is low for the left channel and high for the right channel. Data is
valid on the rising edge of serial clock. The MSB is left-justified
to the frame sync transition but with a delay.
Table 34. S/PDIF Transmitter I
Figure 31
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Table 35. S/PDIF Transmitter Left-Justified Mode
Parameter
Timing Requirement
t
Parameter
Timing Requirement
t
I2SD
LJD
shows the default I
shows the left-justified mode. The frame sync is high
DAI_P20–1
DAI_P20–1
DAI_P20–1
SDATA
SCLK
FS
FS to MSB Delay in I
FS to MSB Delay in Left-Justified Mode
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
DAI_P20–1
DAI_P20–1
DAI_P20–1
2
SDATA
S-justified mode. The frame sync
SCLK
FS
2
S Mode
t
I2SD
MSB
2
S Mode
MSB
t
LJD
MSB–1
Rev. G | Page 37 of 56 | March 2011
MSB–1
Figure 31. Left-Justified Mode
MSB–2
Figure 30. I
MSB–2
2
S-Justified Mode
LEFT/RIGHT CHANNEL
LEFT/RIGHT CHANNEL
LSB+2
LSB+2
LSB+1
LSB+1
LSB
LSB
Nominal
1
Nominal
0
Unit
SCLK
Unit
SCLK

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