MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 17

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

READs
as shown in Figure 6.
vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic READ commands used in the following illus-
trations, auto precharge is disabled.
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid nomi-
nally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 7 shows
general timing for each possible CAS latency setting.
DQS is driven by the DDR SDRAM along with output
data. The initial LOW state on DQS is known as the
read preamble; the LOW state coincident with the last
data-out element is known as the read postamble.
commands have been initiated, the DQs will go
High-Z. A detailed explanation of
out skew),
data window are depicted in Figure 27. A detailed
explanation of
and
Figure 28.
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed
burst or the last desired data element of a longer burst
which is being truncated. The new READ command
should be issued x cycles after the first READ command,
where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architec-
ture). This is shown in Figure 8. A READ command can
be initiated on any clock cycle following a previous
READ command. Nonconsecutive read data is shown
for illustration in Figure 9. Full-speed random read
accesses within a page (or pages) can be performed as
shown in Figure 10.
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
READ bursts are initiated with a READ command,
The starting column and bank addresses are pro-
During READ bursts, the valid data-out element
Upon completion of a burst, assuming no other
Data from any READ burst may be concatenated
t
AC (data-out transition skew to CK) is depicted in
t
QH (data-out window hold), the valid
t
DQSCK (DQS transition skew to CK)
t
DQSQ (valid data-
17
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A11, A12
x16: A0-A9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
x8: A12
BA0,1
CAS#
RAS#
WE#
A10
READ Command
CKE
CK#
CS#
CK
512Mb: x4, x8, x16
Figure 6
HIGH
DON’T CARE
DIS AP
EN AP
BA
CA
DDR SDRAM
©2000, Micron Technology, Inc.
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