MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet

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... NOTE: 1. Supports PC2100 modules with 2-2-2 timing 2. Supports PC2100 modules with 2.5-3-3 timing 3. Supports PC1600 modules with 2-2-2 timing 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’ ...

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... PART NUMBER MT46V128M4TH-xx MT46V128M4TH-xxL MT46V64M8TH-xx MT46V64M8TH-xxL MT46V32M16D1TH-xx MT46V32M16D1TH-xxL MT46V32M16D2TH-xx MT46V32M16D2TH-xxL MT46V32M16D3TH-xx MT46V32M16D3TH-xxL GENERAL DESCRIPTION The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a quad- bank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation ...

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... Random Read Accesses ................................ 21 Terminating a Read Burst ............................ 23 Read to Write ............................................... 24 Read to Precharge ......................................... 25 Writes ................................................................ 26 Write Burst .................................................... 27 Consecutive Write to Write ......................... 28 Nonconsecutive Write to Write .................. 29 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 512Mb: x4, x8, x16 4 Random Writes ............................................ 30 5 Write to Read – Uninterrupting .................. 31 6 Write to Read – Interrupting ....................... 32 7 Write to Read – ...

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... WE# CAS# RAS# REFRESH 13 COUNTER MODE REGISTERS 13 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 2 12 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 FUNCTIONAL BLOCK DIAGRAM 128 Meg x 4 BANK3 BANK2 BANK1 BANK0 ROW- 13 ADDRESS ROW- BANK0 ADDRESS MUX MEMORY 8192 ...

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... LOGIC WE# CAS# RAS# REFRESH 13 COUNTER MODE REGISTERS 13 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 2 11 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 FUNCTIONAL BLOCK DIAGRAM 64 Meg x 8 BANK3 BANK2 BANK1 BANK0 ROW- 13 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 8192 ...

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... REFRESH COUNTER 13 MODE REGISTERS ROW- ADDRESS MUX A0-A12, ADDRESS 15 BA0, BA1 REGISTER 2 10 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 FUNCTIONAL BLOCK DIAGRAM 32 Meg x 16 BANK3 BANK2 BANK1 BANK0 13 ROW- BANK0 ADDRESS MEMORY 8192 LATCH ARRAY & (8,192 x 512 x 32) ...

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... A0–A12 28, 41 10, 11, 13, DQ0–15 54, 56, 57, 59, 60, 62, 63, 65 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 TYPE Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK# ...

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... A13 NOTE pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins deemed importance. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 TYPE I/O Data Input/Output: Data bus for x8 ( and 65 are NC for x4). ...

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... I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins ...

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... Figure 1 Mode Register Definition 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved ...

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... CL = 2.5 DQS DQ Burst Length = 4 in the cases shown Shown with nominal t AC and nominal t DSDQ TRANSITIONING DATA Figure 2 CAS Latency 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 SPEED Operating Mode T2 T2n T3 T3n The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values ...

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... DLL for the purpose of debug or evalua- tion. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 512Mb: x4, x8, x16 ...

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... WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 512Mb: x4, x8, x16 appear following the Operation section; these tables provide current state/next state information ...

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... The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...

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... SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW) ...

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... Operations BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 4. After a row is opened with an ACTIVE command, ...

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... CK and CK#). Figure 7 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble ...

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... READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the programmed order following Shown with nominal t AC, t DQSCK, and t DQSQ. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ T2n NOP NOP ...

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... Three subsequent elements of data-out appear in the programmed order following Three (or seven) subsequent elements of data-out appear in the programmed order following Shown with nominal 6. Example applies only when READ commands are issued to same device. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ ...

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... Three subsequent elements of data-out appear in the programmed order following Three (or seven) subsequent elements of data-out appear in the programmed order following Shown with nominal 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ ...

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... NOTE ( data-out from column n (or column x or column b or column g). 2. Burst length = ( the following burst interrupts the previous indicates the next data-out following respectively. 4. READs are to an active row in any bank. 5. Shown with nominal 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ T2n ...

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... DQSS [MIN] and [MAX] are defined in the section on WRITEs.) 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The ...

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... DQ NOTE data-out from column n. 2. Burst length = 4. 3. Subsequent element of data-out appears in the programmed order following Shown with nominal t AC, t DQSCK, and t DQSQ. 5. BST = BURST TERMINATE command, page remains open. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ T2n 5 BST ...

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... BST command shown can be NOP). 4. One subsequent element of data-out appears in the programmed order following Data-in elements are applied following the programmed order. 6. Shown with nominal 7. BST = BURST TERMINATE command, page remains open. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ T2n ...

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... Three subsequent elements of data-out appear in the programmed order following Shown with nominal t AC, t DQSCK, and t DQSQ. 5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out. 6. PRE = PRECHARGE command; ACT = ACTIVE command. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ ...

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... WRITE burst, as shown in Figure 19. Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 20. Note that only the data-in pairs that are registered 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 x4: A0–A9, A11, A12 t DQSS) is ...

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... DQ DM NOTE data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following uninterrupted burst shown. 4. A10 is LOW with the WRITE command (auto precharge is disabled). 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ WRITE NOP Bank a, Col b ...

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... Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following uninterrupted burst shown. 5. Each WRITE command may be to any bank. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 T1n ...

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... Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following uninterrupted burst shown. 5. Each WRITE command may be to any bank. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 T1n ...

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... NOTE etc. = data-in for column b, etc. 2. b', etc. = the next data-in following DI b, etc., according to the programmed burst order. 3. Programmed burst length = cases shown. 4. Each WRITE command may be to any bank. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 T1n ...

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... The READ and WRITE commands are to the same bank. However, the READ and WRITE commands may be to different devices, in which case t WTR is not required and the READ command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 ...

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... A10 is LOW with the WRITE command (auto precharge is disabled). 6. DQS is required at T2 and T2n (nominal case) to register DM the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last two data elements. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 T1n ...

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... DQS is required at T1n, T2, and T2n (nominal case) to register DM the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last four data elements. WRITE to READ – Odd Number of Data, Interrupting 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1n T2 ...

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... WR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 7. PRE = PRECHARGE command. WRITE to PRECHARGE – Uninterrupting 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1n T2 ...

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... If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 T1n ...

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... If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 T1 T1n ...

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... While in power-down, CKE LOW and a stable clock BA signal must be maintained at the inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DON’T CARE DESELECT command) ...

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... H H NOTE: 1. CKE is the logic state of CKE at clock edge n; CKE n 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND is the command registered at clock edge n, and ACTION n 4. All states and sequences not shown are illegal or reserved. ...

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... Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when Write w/Auto- Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 COMMAND/ACTION X DESELECT (NOP/continue previous operation) ...

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... DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ met, the DDR SDRAM will be in the all banks idle state. t MRD is met, the DDR SDRAM will be in the all banks idle state met, all banks will be in the idle state. 40 ADVANCE ...

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... This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank such a state that the given command is allowable). Exceptions are covered in the notes below. (Notes continued on next page) 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 COMMAND/ACTION X ...

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... READs or WRITEs with auto precharge disabled. 8. Requires appropriate DM masking WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI- NATE must be used to end the READ burst prior to asserting a WRITE command. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 512Mb: x4, x8, x16 t RP has been met ...

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... Input Low (Logic 0) Voltage Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# I/O Reference Voltage 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to ...

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... Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 512Mb: x4, x8, x16 SYMBOL MIN DC – ...

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... SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with t t auto precharge RC(MIN); control inputs change only during Active READ, or WRITE commands. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 ≤ +70° CK(MIN 0mA; OUT ...

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... Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 512Mb: x4, x8, x16 SYMBOL MIN DC – ...

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... SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with t t auto precharge with , RC = RC(MIN); control inputs change only during Active READ, or WRITE commands. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 ≤ +70° RC(MIN); ...

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... ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 ≤ +70° SYMBOL MIN ...

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... SPEED SLEW RATE -7, -75 0.500V / ns -7, -75 0.400V / ns -7, -75 0.300V / ns -7, -75 0.200V / ns -8 0.500V / ns -8 0.400V / ns -8 0.300V / ns -8 0.200V / ns 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 ≤ +70° +2.5V ±0.2V -75 SYMBOL MIN MAX MIN t WPRE 0.25 0.25 t WPRES ...

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... DD rates. Specified values are obtained with minimum cycle time for -7 and - 2.5 for -75 with the outputs open. 11. Enables on-chip refresh and address counters. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 12 properly initialized, and is averaged at the defined cycle rate ...

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... However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/ group will not differ by more than this maxi- mum amount for any given device ...

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... V (V) OUT 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 c) The full variation in driver pull-up current The variation in driver pull-up current within ) can be MIN e) The full variation in the ratio of the maximum t DQSQ. f) The full variation in the ratio of the nominal ...

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... V (V) OUT 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 VIL undershoot: VIL(MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. V 42. Note 42 is not used. ...

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... NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 NOMINAL MINIMUM MAXIMUM LOW 4.6 9.6 -6.1 9.2 18.2 -12 ...

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... NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 NOMINAL NOMINAL MINIMUM MAXIMUM LOW 2.6 5.0 -3.5 5.2 9.9 -6 ...

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... DQs . derived from QHS the lesser clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transitions and is defined minus t DQSQ. x4, x8 Data Output Timing – 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ ...

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... DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7 DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs . x16 Data Output Timing – 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ T2n ...

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... Data Output Timing - T0 CK# CK DQS DQ DM NOTE DSH (MIN DSS (MIN) 3. WRITE command issued at T0. 4. For x16, LDQS controls the lower byte and UDQS controls the upper byte. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ T2n t DQSCK 1 (MAX DQSCK (MIN) t RPRE T2 ...

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... Transmitter 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ (2.3V minimum (1.670V for SSTL2 termination) OH(MIN) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V 1.400V 1.300V 1.275V 1.250V 1.225V 1.200V 1.100V 0.940V Provides margin IN between V (MAX) and (MAX) (0.83V ...

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... PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command AUTO REFRESH command, ACT = ACTIVE command Row Address, Bank Address TIMING PARAMETERS -7 -75 SYMBOL MIN MAX MIN MAX t CH 0.45 0.55 0.45 0. 0.45 0.55 0.45 0. (2. 7 (2) 7 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ Ta0 ( ( ( ( ) ) ) ) ( ( ( ( ...

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... No column accesses are allowed progress at the time power-down is entered. TIMING PARAMETERS -7 -75 SYMBOL MIN MAX MIN MAX t CH 0.45 0.55 0.45 0. 0.45 0.55 0.45 0. (2. 7.5 12 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 POWER-DOWN MODE NOP ...

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... The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands. TIMING PARAMETERS -7 -75 SYMBOL MIN MAX MIN MAX t CH 0.45 0.55 0.45 0. 0.45 0.55 0.45 0. (2. 7 (2) 7 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 AUTO REFRESH MODE VALID ( ( ) ) ( ( ) ) NOP 2 NOP 2 AR ...

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... XSNR is required before any non-READ command can be applied, and is required before a READ command can be applied AUTO REFRESH command. TIMING PARAMETERS -7 -75 SYMBOL MIN MAX MIN MAX t CH 0.45 0.55 0.45 0. 0.45 0.55 0.45 0. (2. 7 (2) 7 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 SELF REFRESH MODE ...

Page 64

... PRE = PRECHARGE, ACT = ACTIVE Row Address Bank Address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. The PRECHARGE command can only be applied Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ ...

Page 65

... NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. The READ command can only be applied Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 BANK READ – WITH AUTO PRECHARGE ...

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... CK (2. 7 (2) 7 0.5 0 0.5 0.5 t DQSH 0.35 0.35 t DQSL 0.35 0.35 t DQSS 0.75 1.25 0.75 1.25 t DSS 0.2 0.2 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ NOP 6 WRITE 2 NOP Col Bank x t RCD t RAS t DQSS (NOM WPRES WPRE and is referenced from ...

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... CK (2. 7 (2) 7 0.5 0 0.5 0.5 t DQSH 0.35 0.35 t DQSL 0.35 0.35 t DQSS 0.75 1.25 0.75 1.25 t DSS 0.2 0.2 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/ NOP 5 WRITE 2 NOP Col Bank x t RCD t RAS t DQSS (NOM WPRE WPRES and is referenced from T5. ...

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... CK (2) 7 0.5 0 0.5 0.5 t DQSH 0.35 0.35 t DQSL 0.35 0.35 t DQSS 0.75 1.25 0.75 1.25 t DSS 0.2 0.2 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 WRITE – DM OPERATION NOP 6 WRITE 2 NOP Col Bank x t RCD t RAS t DQSS ...

Page 69

... PIN # All dimensions in millimeters MAX or typical here noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 (TH) OPTION 66-PIN PLASTIC TSOP (400 MIL) 3.10 11.76 ±0.10 10.16 ± ...

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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00 (TG) OPTION 66-PIN PLASTIC TSOP (400 MIL) SEE DETAIL A 0 ...