MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 12

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

EXTENDED MODE REGISTER
yond those controlled by the mode register; these
additional functions are DLL enable/disable and
output drive strength. These functions are controlled
via the bits shown in Figure 3. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
fied to be SSTL2, Class II. The x16 supports an option
for reduced drive. This option is intended for the
support of the lighter load and/or point-to-point
environments. The selection of the reduced drive
strength will alter the DQs and DQSs from SSTL2, Class
II drive strength to a reduced drive strength, which is
approximately 54% of the SSTL2, Class II drive strength.
Micron will support these x16 options: 1) Full drive
strength only (not programmable), 2) Reduced drive
strength only (not programable), and 3) Program-
mable full or reduced drive strength.
DLL Enable/Disable
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
The extended mode register controls functions be-
The extended mode register must be loaded when
The normal drive strength for all outputs are speci-
The DLL must be enabled for normal operation.
12
NOTE: 1. E14 and E13 (BA0 and BA1) must be “1, 0” to select the
E12
0
–
Extended Mode Register Definition
E11
1 1
14
BA0 BA1
0
–
2. The reduced drive strength option is not supported on
3. The QFC# option is not supported.
0 1
E10
13
0
–
Extended Mode Register (vs. the base Mode Register).
the x4 and x8 versions: and is only available on the D3 version
of the x16 device.
12
E9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A12
0
–
11
E8
A11
0
–
E7
10
0
–
A10
Operating Mode
E6 E5
0
–
9
A9
0
–
8
A8
512Mb: x4, x8, x16
Figure 3
E4
0
–
7
A7 A6 A5 A4 A3
E3
0
–
6
5
E2,
Valid
4
E1,
–
DDR SDRAM
E0
3
QFC
2
E2
A2 A1 A0
0
–
3
DS
Operating Mode
Reserved
Reserved
1
©2000, Micron Technology, Inc.
E1 2
0
1
DLL
ADVANCE
0
E0
0
1
QFC Function
Drive Strength
Reserved
Extended Mode
Register (Ex)
Disabled
Address Bus
Reduced
Normal
Disable
Enable
DLL