MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 11

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, or 2.5 clocks, as shown in Figure 2.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 2
indicates the operating frequencies at which each CAS
latency setting can be used.
operation or incompatibility with future versions may
result.
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
COMMAND
COMMAND
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC and nominal t DSDQ
T0
T0
CAS Latency
Figure 2
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n
11
Operating Mode
MODE REGISTER SET command with bits A7-A12
each set to zero, and bits A0-A6 set to the desired values.
A DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9-A12 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD MODE
REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.
reserved for future use and/or test modes. Test modes
and reserved states should not be used because un-
known operation or incompatibility with future ver-
sions may result.
The normal operating mode is selected by issuing a
All other combinations of values for A7-A12 are
SPEED
-75
-7
-8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAS Latency (CL)
ALLOWABLE OPERATING
512Mb: x4, x8, x16
83 ≤
83 ≤
83 ≤
Table 2
CL = 2
FREQUENCY (MHz)
f
f
f
≤ 133
≤ 100
≤ 100
DDR SDRAM
©2000, Micron Technology, Inc.
83 ≤
83 ≤
83 ≤
ADVANCE
CL = 2.5
f
f
f
≤ 143
≤133
≤125