MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 53

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

NOTES (continued)
38.Reduced Output Drive Curves:
39. The voltage levels used are derived from the
40. V
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
80
70
60
50
40
30
20
10
0
a) The full variation in driver pull-down current from
b) The variation in driver pull-down current
c) The full variation in driver pull-up current from
d) The variation in driver pull-up current within
e) The full variation in the ratio of the maximum
f) The full variation in the ratio of the nominal
0.0
refernced test load. In practice, the voltage levels
obtained from a properly terminated bus will
provide significantly different voltage values.
pulse width ≤ 3ns and the pulse width can not
be greater than 1/3 of the cycle rate.
IH
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure C.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure C.
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure D.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure D.
to minimum pull-up and pull-down current
should be between .71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0
Volt, and at the same voltage and tempera-
ture.
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages
from 0.1V to 1.0 Volt.
overshoot: V
0.5
Pull-Down Characteristics
IH
(MAX) = V
1.0
Figure C
V
OUT
(V)
1.5
DD
Q+1.5V for a
2.0
2.5
53
41. V
42. Note 42 is not used.
43. Note 43 is not used.
44. During initialization, V
45. Note 45 is not used.
46. Note 46 is not used.
47. Note 47 is not used.
48. Random addressing changing 50% of data
49. Random addressing changing 100% of data
50. CKE must be active (high) during the entire time
51. IDD2N specifies the DQ, DQS, and DM to be
52. Whenever the operating frequency is altered, not
-10
-15
-20
-25
-30
-35
-40
-45
-50
-5
0
0.0
VIL undershoot: VIL(MIN) = -1.5V for a pulse
width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate.
equal to or less than V
V
even if V
minimum of 42 ohms of series resistance is used
between the V
changing at every transfer.
changing at every transfer.
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until
driven to a valid high or low logic level. IDD2Q
is similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
including jitter, the DLL is required to be reset,
and followed by 200 clock cycles.
DD
TT
may be 1.35V maximum during power up,
and V
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
REF later.
DD
0.2
DDQ
/V
TT
DDQ
must track each other.
Pull-Up Characteristics
supply and the input pin.
512Mb: x4, x8, x16
are 0 volts, provided a
0.4
V
Figure D
DD
DD
Q - V
DDQ
+ 0.3V. Alternatively,
OUT
, V
(V)
DDR SDRAM
0.6
TT
, and V
©2000, Micron Technology, Inc.
ADVANCE
REF
0.8
must be
1.0