SPC5121YVY400BR Freescale, SPC5121YVY400BR Datasheet - Page 75

• Manufacturer Part Number: SPC5121YVY400BR
• Manufacturer: Freescale

Specifications of SPC5121YVY400BR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.3.24
The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream.
Figure 56
4
4.1
Power sequencing between the 1.4 V power supply VDD_CORE and the remaing supplies is required to prevent excessive
current during power up phase.
The recommended power sequence is as follows:
4.2
Each of the independent PLL power supplies require filtering external to the device. The following drawing
recommendation for the required filter circuit.
Each circuit should be placed as close as possible to the specific AV
nearby circuits.
All traces should be as low impedance as possible, especially ground pins to the ground plane.
Freescale Semiconductor
Parameter
f
PIX_CK
t
t
•
•
•
•
•
DSU
DHD
Use 12V/millisecond or slower time for all supplies.
Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, AVDD_FUSERD, USB
PHY & SATA PHY supplies first in any order and then power up VDD_CORE. If required AVDD_FUSEWR should
be powered up afterwards.
All the supplies must reach the specified operating conditions before the PORESET can be released.
For power down, drop AVDD_FUSEWR to 0V first, drop VDD_CORE to 0V, and then drop all other supplies.
VDD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC or PLL_AVDDs by more than 0.4 V at any
time, including power-up.
shows the VIU interface timing and
VIU_PIX_CLK
VIU_DATA[9:0]
System Design Information
Power Up/Down Sequencing
System and CPU Core AVDD Power Supply Filtering
VIU Pixel Clock Frequency
VIU Data Setup Time
VIU Data Hold Time
VIU
Description
f
Table 51. VIU Interface Timing Parameters
PIX_CLK
Figure 56. VIU Interface Timing Diagram
MPC5121E/MPC5123 Data Sheet, Rev. 3
Table 51
lists the timing parameters.
Min
2.5
2.5
-
t
DHD
DD
pin being supplied to minimize noise coupled from
Typ
t
DSU
-
-
-
Max
83
-
-
System Design Information
Unit
MHz
ns
ns
Figure 57
SpecID
A24.1
A24.2
A24.3
is a
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