SPC5121YVY400BR Freescale, SPC5121YVY400BR Datasheet - Page 26

• Manufacturer Part Number: SPC5121YVY400BR
• Manufacturer: Freescale

Specifications of SPC5121YVY400BR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Electrical and Thermal Characteristics
3.2.4
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
26
1
2
3
4
1
2
Sys PLL VCO frequency
Sys PLL VCO output jitter (Dj),
peak to peak / cycle
Sys PLL VCO output jitter (Rj), rms
1 sigma
Sys PLL relock time - after power
up
Sys PLL relock time - when power
was on
e300 frequency
e300 PLL VCO frequency
e300 PLL input clock frequency
e300 PLL input clock cycle time
e300 PLL relock time
The SYS_XTALI frequency and PLL Configuration bits must be chosen such that the resulting system
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
This represents total input jitter - short term and long term combined. Two different types of jitter can exist
on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic
jitter is passed into and through the PLL to the internal clock circuitry.
PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and
CORE_SYSCLK are reached during the power-on reset sequence.
PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled
and subsequently re-enabled during sleep modes.
The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies,
CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies in
f
PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and
CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep modes.
VCOcore
3
e300 Core PLL Electrical Characteristics
4
Characteristic
Characteristic
/2).
1
2
1
1
Table
Table 14. System PLL Specifications
16. There is a hard coded relationship between f
MPC5121E/MPC5123 Data Sheet, Rev. 3
Table 15. e300 PLL Specifications
f
f
f
t
VCOjitterDj
VCOjitterRj
f
CSB_CLK
CSB_CLK
f
VCOcore
VCOsys
Sym
t
t
Sym
f
t
lock1
lock2
core
lock
Min
Min
400
200
400
50
—
—
—
—
—
5
Typical
Typical
—
—
—
—
—
—
—
—
—
—
Max
Max
800
200
170
400
800
200
200
40
12
20
core
and f
MHz
MHz
MHz
MHz
Unit
Unit
VCOcore
μs
μs
μs
ps
ps
ns
Freescale Semiconductor
(f
SpecID
SpecID
core
O3.3
O3.4
O3.5
O3.6
O3.7
O4.1
O4.3
O4.4
O4.5
O4.6
=